ECM-3612

 

Signal

 

Signal Description

 

 

 

 

This is an active low signal driven by the current master to indicate an I/O read

 

 

 

 

 

operation. I/O mapped devices using this strobe for selection should decode

 

 

IOR#,

 

 

addresses SA [15:0] and AEN.

 

 

IOW#

 

 

Additionally, DMA devices will use IOR# in conjunction with DACKn# to decode a

 

 

 

 

 

DMA transfer from the I/O device. The current bus master will drive this line with a

 

 

 

 

 

tri-state driver.

 

 

 

 

 

This is an active low signal driven by the permanent master to indicate a memory

 

 

 

 

read operation in the first 1MB of system memory. Memory mapped devices

 

SMEMR#,

 

using this strobe should decode addresses SA [19:0] only. If an alternate master

 

SMEMW#

 

drives MEMR#, the permanent master will drive SMEMR# delayed by internal

 

 

 

 

logic. The permanent master ties this line to VCC through a pull-up resistor to

 

 

 

 

ensure that it is inactive during the exchange of bus masters.

 

 

 

 

 

 

 

 

 

This is an active low signal driven by the current master to indicate a memory

 

MEMR#,

 

 

read operation. Memory mapped devices using this strobe should decode

 

 

 

addresses LA [23:17] and SA [19:0]. All bus masters will drive this line with a

 

MEMW#

 

 

 

 

 

tri-state driver. The permanent master ties this line to VCC through a pull-up

 

 

 

 

 

 

 

 

resistor to ensure that it is inactive during the exchange of bus masters.

 

 

 

 

This is an active low signal driven by an I/O-mapped PC-AT/PC104 adapter

 

IOCS16#

 

indicating that the I/O device located at the address is a 16-bit device. This open

 

 

collector signal is driven, based on SA [15:0] only (not IOR# and IOW#) when

 

 

 

 

 

 

 

 

AEN is not asserted.

 

 

 

 

 

 

 

 

 

This is an active low signal driven by a memory mapped PC-AT/PC104 adapter

 

MEMCS16#

 

 

indicating that the memory device located at the address is a 16-bit device. This

 

 

 

 

open collector signal is driven, based on LA [23:17] only.

 

 

 

 

This signal is an active low open-collector signal asserted by a 16-bit memory

 

OWS#

 

mapped device that may cause an early termination of the current transfer. It

 

 

should be gated with MEMR# or MEMW# and is not valid during DMA transfers.

 

 

 

 

 

 

 

 

IOCHRDY precedes 0WS#.

 

 

 

 

 

 

 

 

 

This is an active high signal driven inactive by the target of either a memory or an

 

 

IOCHRDY

 

 

I/O operation to extend the current cycle. This open collector signal is driven

 

 

 

 

based on the system address and the appropriate control strobe. IOCHRDY

 

 

 

 

 

 

 

 

 

 

precedes 0WS#.

 

 

 

 

 

This is an active low signal driven active by a PC-AT/PC104 adapter detecting a

 

IOCHCK#

 

fatal error during bus operation. When this open collector signal is driven low it

 

 

 

 

will typically cause a nonmaskable interrupt.

 

 

 

 

 

 

44 ECM-3612 User’s Manual