User’s Manual
3.5.3.3 Bank Interleave
Enables to set the interleave mode of the SDRM interface which allows banks of SDRAM to alternate their refresh and access cycles.
The choices: Disabled, 2 Bank, 4 Bank.
3.5.3.4 Memory Hole
When this item is enabled, ISA ROM will be mapped to
The choices: Disabled,
3.5.3.5 P2C/C2P Concurrency
CPU bus will be occupied during the entire PCI operation period when disabled. The choices: Enabled, Disabled.
3.5.3.6 System BIOS Cacheable
This feature is only valid when the system BIOS is shadowed. It enables or disables the caching of the system BIOS ROM at
3.5.3.7 Video RAM Cacheable
This feature is only valid when the video BIOS is shadowed. It enables or disables the caching of the video BIOS ROM at
The choice: Enabled, Disabled.
3.5.3.8 Frame Buffer Size
Select the size of onboard video controller’s frame buffer. The buffer size are share from system memory unit.
The choices: 2MB, 4MB, 8MB, 16MB, 32MB.
3.5.3.9 AGP Aperture Size
Select the size of Accelerated Graphics Port (AGP) aperture. The aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host cycles that hit the aperture range are forwarded to the AGP without any translation.
The choices: 4MB,8MB,16MB.32MB, 64MB,128MB.
3.5.3.10
This item allows you to enable / disable the
The choices: Enabled, Disabled.