Cisco Systems MGX-FRSM-2T3E3 manual Bit Error Rate Testing on an Unchannelized T3 or E3 Frsm

Bit Error Rate Testing on an Unchannelized T3 or E3 FRSM

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addchanloop and delchanloop are standard user commands for looping on a channel.

tstcon checks the integrity of a connection.

tstdelay measures the round trip delay on a connection.

Bit Error Rate Testing on an Unchannelized T3 or E3 FRSM

The MGX 8850 switch can perform a bit error rate test (BERT) on one active line at a time on the MGX-FRSM-2T3 or MGX-FRSM-2E3. This type of testing disrupts service because it requires the tested path to be in loopback mode. You can configure a BERT session and perform related tasks through the CiscoView application or the CLI.

The MGX 8850 bus structure supports one BERT session per upper or lower bay of the card cage, so the switch can run a maximum of two sessions at once. When you specify the target slot through the CiscoView application or the acqdsx3bert command on the CLI, the system determines if a BERT configuration already exists in the bay that has the specified slot. If no BERT configuration exists in the bay, the display presents a menu for the BERT parameters.

The CLI commands (whose functions correspond to CiscoView selections) are:

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acqdsx3bert to determine if other BERT sessions exist in the bay

cnfdsx3bert to specify a pattern for the BERT test

startdsx3bert to start a BERT test (after resetting BERT counters)

moddsx3bert to inject multi-rate errors into the BERT bit stream

dspdsx3bert to display the parameters and results of the current test

deldsx3bert to end the current test (and retain the values in the BERT counters)

See the Cisco MGX 8850 Wide Area Edge Switch Command Reference for command details.

Note When a BERT session begins, all the connections on the line go into alarm and return to normal when you end the test. Consequently, the test may result in a large number of traps and other types of traffic (such as AIS).

Card and Service Configuration 6-35