Cisco Systems UBR924 - page 24

show controllers cable-modem
24 Cisco IOS Release 12.0(5)T
TX PD ring:
tx_head_pd
tx_tail_pd
ehdr
Indicates the memory location of the beginning of buffer information for the transmit
packet descriptor ring.
Indicates current head packet descriptor.
Indicates current tail packet descriptor.
Extended MCNS header.
MIB Statistics:
DS fifo full Number of times the downstream input first-in first-out (FIFO) buffer became full on
the Cisco uBR924.
rerequests Number of times a bandwidth request generated by the Cisco uBR924 was not
responded to by the CMTS.
DS mac msg overruns Number of times the Cisco uBR924’s DMA controller had a downstream MAC
message and there were no free MAC message buffer descriptors to accept the message.
DS data overruns Number of times the Cisco uBR924’s DMA controller had downstream data and there
were no free data PDU buffer descriptors to accept the data.
Qualified maps Number of times a MAP message passed all filtering requirements and was received by
the Cisco uBR924.
Qualified syncs Number of times a timestamp message was received by the Cisco uBR924.
CRC fails Number of times a MAC message failed a cyclic redundancy (CRC) check.
HDR chk fails Number of times a MAC header failed its 16-bit CRC check. The MAC header CRC is a
16-bit Header Check Sequence (HCS) field that ensures the integrity of the MAC
header even in a collision environment.
Data pdus Total number of data PDUs (protocol data units) of all types received by the
CiscouBR924.
Mac msgs Number of MAC messages received by the Cisco uBR924.
Valid hdrs Number of valid headers received by the Cisco uBR924, including PDU headers, MAC
headers, and headers only.
Global control and status: Used to reset the BCM3300 chip.
interrupts: Hexadecimal values of the pending IRQ interrupt and IRQ mask.
Table2 Show Controllers Cable-Modem Field Descriptions (continued)
Field Description