Clevo D410E manual REQ2#, REQ0#, GNT2#, GNT0#, Par, Susb#

Schematic Diagrams

962 (PCI/IDE/HyperZip) 1 of 4

19,20,25 AD[0..31]

AD[0..31]

IDESAA[0..2]

IDESAA[0..2]

14

IDECS#A[0..1]

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

IDECS#A[0..1]

14

IDESAB[0..2]

+1.8VS

IDESAB[0..2]

14

IDECS#B[0..1]

IDECS#B[0..1]

14

R118

0

BGA2A

J5 J4 H2 H1 J3 K4 J2 J1 K5 K2 L3 K1 L1 L4 L5 L2 N5 P2 P3 P4 R2 R3 R1 T1 P5 T2 U1 U2 T3 R5 U3 V1

C151

+3VS

REQ4#

F1

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

IDEAVDD

Y4

C150

Y3

0.01UF

0.1UF

REQ3#

F2

PREQ#4

IDEAVSS

RP32

25

REQ2#

REQ2#

E1

PREQ#3

ICHRDYA

W10

ICHRDYA

ICHRDYA

14

FRAME#

1

10

REQ1#

H5

PREQ#2

V10

IDEREQA

1

10

TRDY#

PREQ#1

IDREQA

IDEREQA

14

REQ2#

2

9

19

REQ0#

REQ0#

F3

PCI

Y11

IDEIRQA

2

9

PREQ#0

IIRQA

IDEIRQA

14

SERR#

3

8

IRDY#

U12

CBLIDA

STOP#

4

3

8

7

PLOCK#

GNT4#

H3

CBLIDA

CBLIDA

14

5

4

7

6

DEVSEL#

GNT3#

G1

PGNT#4

V11

MIDEIOR#A

R98

10

IDEIOR#A

IDEIOR#A

14

5

6

25

GNT2#

GNT2#

G2

PGNT#3

IIOR#A

Y9

MIDEIOW#A

R104

22

IDEIOW#A

10P8R-2.7K

GNT1#

G3

PGNT#2

IIOW#A

Y10

MIDACK#A

R103

22

IDACK#A

IDEIOW#A

14

19

GNT0#

GNT0#

H4

PGNT#1

IDACK#A

IDACK#A

14

Diagrams

PGNT#0

T11

MIDESAA2

R360

33

IDESAA2

+3VS

C/BE#3

IDSAA2

19,25

PAR

K3

PAR

U11

MIDESAA1

R363

33

IDESAA1

IDSAB2

19,20,25 C/BE#3

C/BE#2

M4

C/BE#3

IDSAA1

W11

MIDESAA0

R97

33

IDESAA0

RN5

19,20,25 C/BE#2

C/BE#1

P1

C/BE#2

IDSAA0

INTD#

8

1

19,20,25 C/BE#1

C/BE#0

R4

C/BE#1

T12

MIDECS#A1

R358

33

IDECS#A1

INTA#

7

2

19,20,25 C/BE#0

C/BE#0

IDECSA#1

V12

MIDECS#A0

R91

33

IDECS#A0

INTB#

6

3

9,10,30

INTA#

INTA#

E3

INT#A

IDECSA#0

INTC#

5

4

INTB#

F4

INT#B

ICHRDYB

Sheet 13 of 41

8P4R-2.2K

RN6

19

INTC#

INTC#

E2

ICHRDYB

W17

ICHRDYB

14

INTD#

G4

INT#C

Y17

IDEREQB

REQ0#

8

1

25,30

INTD#

INT#D

IDREQB

T16

IDEIRQB

IDEREQB

14

REQ3#

7

2

19,20,25 FRAME#

FRAME#

M3

IIRQB

U17

CBLIDB

IDEIRQB

14

FRAME#

CBLIDB

CBLIDB

14

962 (PCI/IDE/

REQ4#

6

3

19,25

STOP#

IRDY#

M1

STOP#

IDE

IIOW#B

V16

MIDACK#B

R87

22

IDACK#B

IDEIOW#B

14

REQ1#

5

4

19,20,25 IRDY#

TRDY#

M2

IRDY#

T14

MIDEIOR#B

R352

10

IDEIOR#B

19,20,25 TRDY#

TRDY#

IIOR#B

IDEIOR#B

14

8P4R-4.7K

STOP#

N4

W16

MIDEIOW#B

R90

22

IDEIOW#B

HyperZip)

GNT1#

R390

4.7K

19,25 DEVSEL#

SERR#

M5

DEVSEL#

IDACK#B

T15

MIDESAB1

R351

33

IDESAB1

IDACK#B

14

GNT4#

R389

4.7K

DEVSEL#

N1

IDSAB1

GNT3#

R388

4.7K

19,25

SERR#

PAR

N3

SERR#

Y18

MIDESAB2

R80

33

IDESAB2

B.Schematic

1 of 4

PLOCK#

N2

PLOCK#

IDSAB0

V17

MIDESAB0

R86

33

IDESAB0

150_1%

0.1UF

SZCMP_N

N18

V15

IDEDB1

IDEDA[0..15]

14

VDDZCMP

IDB0

4

PCICLK961

PCICLK961

33

Y2

PCICLK

IDECSB#1

U16

MIDECS#B1

R349

33

IDECS#B1

PCIRST#

R125

C3

W18

MIDECS#B0

R79

33

IDECS#B0

9,10,14,20,22,24,30 PCIRST#

PCIRST#

IDECSB#0

IDEDA0

962-1

IDA0

U10

V9

IDEDA1

IDA1

W8

IDEDA2

ZCLK1

IDA2

T9

IDEDA3

+1.8VS

4

ZCLK1

V20

ZCLK

IDA3

Y7

IDEDA4

IDA4

V7

IDEDA5

9

ZSTB0

ZSTB0

N19

IDA5

Y6

IDEDA6

R76

9

ZSTB#0

ZSTB#0

ZSTB0#

IDA7

W6

IDEDA8

9

ZSTB1

ZSTB1

K20

ZSTB1

IDA8

U8

IDEDA9

C460

ZSTB#1

K19

IDA9

W7

IDEDA10

9

ZSTB#1

ZSTB1#

IDA10

150_1%

0.1UF

V8

IDEDA11

SZVREF

ZUREQ

IDA11

U9

IDEDA12

9

ZUREQ

N16

ZUREQ

IDA12

Y8

IDEDA13

ZDREQ

N17

IDA13

T10

IDEDA14

R77

9

ZDREQ

ZDREQ

IDA14

W9

IDEDA15

IDA15

SVDDZCMP

IDEDB0

C459

R19

Y16

N10

SZCMP_P

ZCMP_N

IDB1

U14

IDEDB2

R18

ZCMP_P

IDB2

W14

IDEDB3

SVSSZCMP

P18

IDB3

V13

IDEDB4

10MIL

VSSZCMP

IDB4

T13

IDEDB5

SZ1XAVDD

IDB5

Y13

IDEDB6

U20

Z1XAVDD

IDB6

Y12

IDEDB7

SZ1XAVSS

U19

IDB7

W12

IDEDB8

SZ4XAVDD

Z1XAVSS

HyperZip

IDB8

W13

IDEDB9

+3V

T20

VZREF

IDB9

U13

IDEDB10

SZVREF

P20

IDB13

Y15

IDEDB14

SZ4XAVSS

T19

Z4XAVDD

IDB10

Y14

IDEDB11

Z4XAVSS

IDB11

V14

IDEDB12

R20

IDB12

W15

IDEDB13

ZVSSREF

ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15

IDB14

U15

IDEDB15

+3V

IDB15

IDEDB[0..15]

14

R366

R365

330K

10K

C146

M18 M19 M17 M16 M20 L16 L20 L18 K18 J20 K17 K16 H20 J18 H19 H18

L87

SIS962

U7

+1.8VS

SUSB#

0.1UF

ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15

FCM1608K121

24,28

SUSB#

1

14

CLR1#

VCC

1

2

35.64mA

R75

3

6

2

5

T

SVDDZCMP

D1

Q1

56 SZCMP_N

T

4

CLK1

Q1#

T

C462

C461

PR1#

9

ZAD[0..15]

C444

PRST#

R74

56 SZCMP_P

C514

0.1UF

13

CLR2#

Q2

9

PRST#

19,24,25

10UF/10V

0.1UF

0.01UF

12

8

T

SVSSZCMP

PCIRST#

D2

Q2#

Analog Power supplies of Transzip

11

7

10

CLK2

GND

N17

10MIL

PR2#

function for 96X Chip.

C513

L27

0.1UF(R)

74LVC74

+3VS FCM1608K121

+3VS

L86

1

2

6.49mA

SZ1XAVDD

FCM1608K121

7.92mA

1

2

SZ4XAVDD

C122

C129

Q35

C128

C440

C458

C443

PCIRST#

0(R) PRST#

R684

0(R)

S

D

R685

10UF/10V

0.1UF

0.01UF

G

N11

10MIL

SZ1XAVSS

10UF/10V

0.1UF

0.01UF

N16

10MIL

SZ4XAVSS

2N7002(R)

S3AUXSW#

S3AUXSW# 6,28

B - 14 962 (PCI/IDE/HyperZip) 1 of 4 (71-M4000-D03)