Schematic Diagrams

B - 8 M645DX (& CRT Out) 3 of 4 (71-M4000-D03)

B.Schematic Diagrams

M645DX (& CRT Out) 3 of 4

+3VS
+1.8VS
+1.8VS
+3VS
+3VS
+1.8VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+5VS +5VS
+3VS
+5VS +5VS
+5V+5VS
INTA# 10,13,30
PCIRST# 10,13,14,20,22,24,30
REFCLK0 4
ZCLK04
ZUREQ13
ZDREQ13
ZSTB013 ZSTB#013
ZSTB113 ZSTB#113 ZAD[0..15]13
PWRGD 15,26,29
AUXOK 15,24,27,28
VSY30
HSY30
VGADDCDATA30
VGADDCCLK30
R30
G30
B30
REFCLK0
R-OUT
G-OUT
B-OUT
Z0801
HSYNC
Z0802
VSYNC
DDC1CLK
DDC1DATA
INTA#
Z1XAVDD
PWRGD
PCIRST#
AUXOK
CSYNC
RSYNC
LSYNC
RSYNC
PWRGD
AUXOK
ENTEST
ZAD10
ZSTB0
ZAD12
ZAD6
ZSTB#0
ZAD8
ZSTB#1
ZCMP_P
ZAD15
ZCLK0
ZAD14
ZAD9
ZAD1
ZAD0
ZUREQ
ZDREQ
ZAD7
ZVREF
ZAD2
ZAD13
ZAD11
ZAD5
ZAD3
ZSTB1
ZAD4
TRAP1
TRAP0
TMODE2
TMODE1
TMODE0
DLLEN#
ENTEST
ECLKAVSS
ECLKAVDD
DCLKAVDD
VVBWN
DACAVSS
VRSET
DACAVDD
VCOMP
Z1XAVSS
Z4XAVSS
Z4XAVDD
ZCMP_N
VDDZCMP
VSSZCMP
ZAD[0..15]
MID1_10
FGRN_10
FBLU_10
DDC1CLK
VSYNC
DDC1CLK
HSYNC
DDC1DATA
VS_10
FRED_10
VSYNC
HSYNC
DDC1DATA
MID3_10
HS_10
B
R
G
GOUT
BOUT
ROUT
ROUT
GOUT
BOUT
R754 0(R)
R753 0
T
D35
DA221(R)
3 2
1
T
D34
DA221(R)
3 2
1
T
R528 33
T
L52
FCM1608K121
1 2
T
N12
T
L22
FCM1608K121
1 2
T
N6
T
C94
0.01UF
C400
0.1UF
C399
0.1UF
C97
0.01UF
C413
0.01UF
N1
L9
FCM1608K121
1 2
L10
FCM1608K121
1 2
C287
0.01UF
C271
0.1UF
C442 0.1UF
C428 0.1UF
C87
10UF/10V
C95
0.1UF
C22
0.1UF
C21
0.01UF
R230 33(R)
C19 0.1UF
C18
0.1UF
C17
1UF
C266
10UF/10V
C20 0.1UF
C265
10UF/10V
C13
10UF/10V
R234 4.7K
R229 100(R)
R233 4.7K
R231 100(R)
R49 56
R46
150_1%
R47
150_1%
R232 33(R)
R532
33
C93
10UF/10V
R533
33
C96
0.1UF
Q27
2N7002
G
S D
L24
FCM1608K121
1 2
R16 130_1%
BGA1C
SIS M650
C15
A12
B13
A13
F13
E13
D13
D12
B11
E12
A11
F12
E14
D14
F14
B12
C12
C13
C14
B15
A15
B14
A14
F10
E11
C11
F11
A10
D11
E10
Y3
W4
W6
V2
V1
W1
W2
V5
U4
U2
V6
U3
T4
R3
T5
T6
R2
R6
R1
R4
P4
N3
P5
P6
N1
N6
N2
N4
P1
P3
T3
T1
U6
U1
V3
VOSCI
ROUT
GOUT
BOUT
HSYNC
VSYNC
VGPIO0
VGPIO1
INT#A
CSYNC
RSYNC
LSYNC
VCOMP
VRSET
VVBWN
DACAVDD1
DACAVSS1
DACAVDD2
DACAVSS2
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
ENTEST
DLLEN#
TESTMODE0
TESTMODE1
TESTMODE2
TRAP1
TRAP0
PCIRST#
PWROK
AUXOK
Z4XAVDD
Z4XAVSS
Z1XAVDD
Z1XAVSS
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
ZVREF
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZSTB1
ZSTB#1
ZSTB0
ZSTB#0
ZUREQ
ZDREQ
ZCLK
R534
6.8K
L85
FCM1608K121
1 2
R530
4.7K
N15 Q28
2N7002
G
S D
C414
0.1UF
R531
4.7K
N7
R529 33
T
Q25
2N7002
G
S D
T
Q26
2N7002
G
S D
R48 56
R535
6.8K
C415
10UF/10V
R209
2.2K(R)
C8
22P
D3
DA204U
C
A
AC
C4
220P
R199
75
T
C3
220P
T
D1 F01J2E
AC
L44
FCM1608K121
1 2
C243
22P
VJVGA1
CEN/VGA DSUB
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
17
D21
DA204U
C
A
AC
C245
22P
R200
75
C242
22P L43 FCM1608K121
1 2
R5 FCM1608K121
R4 FCM1608K121
L45 FCM1608K121
1 2
R3 FCM1608K121
L6 FCM1608K121
1 2
C5
220P
R201
75
R693 0
R207
2.2K(R)
C244
220P
D2
DA204U
C
A
AC
R208
4.7K(R)
C7
22P
C6
22P
R210
4.7K(R)
R692 0(R)
R698 0(R)
R697 0(R)
R696 0(R)
R695 0
R694 0
R691 0(R)
R690 0(R)

M650-3

VGA
HyperZip
DLLEN#
DRAM_SEL
TRAP0
TRAP1
SDR
LSYNC
CSYNC
RSYNC
1(DDR)
(30~50K Ohm)Default
DDR 0
1
0
embedded pull-low
0
0 yes
disable PLL yes
1
NB debug mode
0
yes
0
normal
NOTE: This page is for universal PCB design( suitable for both 645 or 650)
NB Hardware Trap Table
enable panel link
enable VGA interface
enable PLL
TV selection, NTSC/PAL(0/1)
enable VB
35.4mA
6.49mA
7.92mA
84.8mA
7.57mA
18.07mA
20MIL
10MIL
10MIL
10MIL
20MIL
10MIL
Sheet 7 of 41
M650 & CRT Out
3 of 4