Clevo D410E manual Sheet 22 of 41 LPC Super I/O, PD0..7

Schematic Diagrams

LPC Super I/O

SA0

12

U1

13

SD0

A0

O0

SA1

11

14

SD1

SA2

10

A1

O1

15

SD2

SA3

9

A2

O2

17

SD3

SA4

8

A3

O3

18

SD4

SA5

7

A4

O4

19

SD5

SA6

6

A5

O5

20

SD6

SA7

5

A6

O6

21

SD7

+3VS

SA8

27

A7

O7

SA9

26

A8

SA10

23

A9

SA11

25

A10

SA12

4

A11

R228

+5VS

SA13

28

A12

+5VS

10K

SA14

29

A13

SA15

3

A14

FLASH#

1

U20

5

R227

1K

SA16

2

A15

VCC

32

IN

VCC

BIOSCS#

22

A16

30

SA17

MEMW#

CE

A17

2

MEMR#

24

IN

SA18

1

OE

C270

3

GND

OUT

4

WBIOS#

31

VPP

GND

16

0.1UF

PGM

TC7S32F

MX29F004

C269

0.1UF

L41

FIRVCC

+3VS

FCM2012V121

C237

4 3 2 1

4 3 2 1

4.7U(0805)

RN7

RN8

8P4R-18

8P4R-18

R503

R506

FIRGND

5 6 7 8

5 6 7 8

4.7K(R)

47K

		C240
10	U35	1000P

IRRX

8

RXD

LEAD

FIRGND

IRMODE

3

FIR_SEL

MDO

4

R504

2.2K

IRTX

9

TXD

MD1

5

R505

2.2K

R507

11

GNDPAD

AGNDD

NC

GND

VCC

4.7K

6

7

2

1

HSDL-3602

JA2

1

2

C677

0.1UF

SHORT-A

FIRGND

T

C238

0.047U

C239

10UF/10V

FIRVCC

+5VS

SA6

RP58

1

10

15,24 LPC_AD[0..3] LPC_AD[0..3]

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

4	PCICLKIO	PCICLKIO
		PCIRST#
9,10,13,14,20,24,30	PCIRST#
		LPC_FRAME#
15,24 LPC_FRAME#
		LPC_DRQ#
15	LPC_DRQ#
		R381	47K
	+3VS
		BID0
15,19,24 SERIRQ		SERIRQ
		FLASH#
4	SIO48M	SIO48M
14	DISKCHG#	DISKCHG#
		HDSEL#
14	HDSEL#
		RDATA#
14	RDATA#
		WRPRT#
14	WRPRT#
		TRK0#
14	TRK0#	WGATE#
14	WGATE#
		WDATA#
14	WDATA#
		STEP#
14	STEP#	DIR#
14	DIR#
		DRV0#
14	DRV0#
		MTR0#
14	MTR0#
		INDEX#
14	INDEX#
		3MODE#
14	3MODE#

T

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

FIRGNDSA14 SA15 SA16 SA17 SA18

T

		+3VS
							C530	C539	C529
	U8	14	39	63	88		0.1UF	0.1UF	0.1UF							PD[0..7]		PD[0..7] 23
15	LAD0	VDD VDD VDD VDD						PD0/INDEX#		52	PD0
16										50	PD1
17	LAD1							PD1/TRK0#		48	PD2
18	LAD2							PD2/WP#		46	PD3
	LAD3							PD3/RDATA#		45	PD4
8	LCLK							PD4/DSKCHG#		44	PD5
9								PD5/MSEN0		43	PD6
12	LRESET#							PD6/DRATE0		42	PD7
6	LFRAME#	PC87393						PD7/MSEN1		36	PSLCT						+3VS
	LPCPD#							PNF/XRDY
11	LDRQ#									35			R400			4.7K
7
	CLKRUN#/GPIO36							SLCT/WGATE#									PSLCT	23
10	SERIRQ							PE/WDATA#		37	PPE						PPE	23
19										40	PBUSY
	SMI#/GPIO35						BUSY_WAIT#/MTR1#			41	PACK#						PBUSY	23
20								ACK#/DR1#		47	PSLIN#						PACK#	23
	CLKIN						SLIN#_ASTRB#/STEP#			49	PINIT#						PSLIN#	23
								INIT#/DIR#		51	PPERR#						PINIT#	23
21								ERR#/HDSEL#		53	PATFD#						PPERR#	23
22	DSKCHG#						AFD#_DSTRB#/DENSEL			54	PSTB#						PATFD#	23
23	HDSEL#							STB#_WRITE#									PSTB#	23
	RDATA#
24
	WP#									55		DCDA#
25																	DCDA#	23
26	TRK0#								DCD1#	56		DSRA#
	WGATE#								DSR1#								DSRA#	23
27	WDATA#								SIN1	57		SINA					SINA	23
28										58		RTSA#
29	SETP#							RTS1#/TEST		59		SOUTA					RTSA#	23
30	DIR#							SOUT1/XCNF0		60		CTSA#					SOUTA	23
31	DR0#								CTS1#	61		DTRA					CTSA#	23
32	MTR0#						DTR1#_BOUT1/BADDR			62		RIA#					DTRA	23
33	INDEX#								RI1#								RIA#	23
	DENSEL
34
	DRATE0/IRSL2									70		IRTX
									IRTX	69		IRRX
95	XA0/GPIO20								IRRX1	68		IRMODE
94								IRRX2_IRSL0		67			T
	XA1/GPIO21								IRSL1						0(R)
93										66	R393						PME#	19,23,24,25
92	XA2/GPIO22						IRSL3/PWUREQ#
	XA3/GPIO23
91
	XA4/GPIO24/XSTB0#									3	SD0
90
87	XA5/XSTB1#/XCNF2						XD0/GPIO00/JOYABTN1			2	SD1
86	XA6/GPIO26/PRIQA/XSTB2#						XD1/GPIO01/JOYBBTN1			1	SD2
85	XA7/GPIO27/PIRQB						XD2/GPIO02/JOYAY			100	SD3
84	XA8/GPIO30/PIRQC						XD3/GPIO03/JOYBY			99	SD4
83	XA9/GPIO31/MTR1#/PIRQD						XD4/GPIO04/JOYBX			98	SD5
82	XA10/GPIO32/XIORD#/MDRX						XD5/GPIO05/JOYAX			97	SD6
81	XA11/GPIO33/XIOWR#/MDTX						XD6/GPIO06/JOYBBTN0			96	SD7
80	XA12/GPIO10/JOYABTN1/RI2#						XD7/GPIO07/JOYABTN0
	XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2									4	MEMW#
79
78	XA14/GPIO12/JOYAY/CTS2#							XWR#/XCNF1		5	MEMR#
77	XA15/GPIO13/JOYBY/SOUT2						XRD#/GPIO34/WDO#			73			TBID1
76	XA16/GPIO14/JOYBX/RTS2#				XIOWR#/XCS1#/MTR1#/DRATE0					71
75	XA17/GPIO15/JOYAX/SIN2					XIORD#/GPIO37/IRSL2/DR1#				72				BIOSCS#
74	XA18/GPIO16/JOYBBTN0/DSR2#					XCS0#/DR1#/XDRY/GPIO25
	XA19/DCD2#/JOYABTN0/GPIO17
		VSS VSS VSS VSS
	PC87393	13	38	64	89

Sheet 22 of 41 LPC Super I/O

B.Schematic Diagrams

SA7	2	1	10	9		SA4
SA8	3	2	9	8		SA3
SA9	4	3	8	7		SA2
	5	4	7	6		SA10
		5	6				+3VS
		10P8R-8.2K
		RP57					RN13	8P4R-10K
SA14	1	1	10	10			8	1	INDEX#
SA15	2			9		SA13	7	2	TRK0#
SA16	3	2	9	8		SA12	6	3	RDATA#
SA17	4	3	8	7		SA11	5	4	DISKCHG#
	5	4	7	6		SA18
		5	6
		10P8R-8.2K
		RP59					RN12	8P4R-10K
SD0	1	1	10	10			8	1	BIOSCS#
SD1	2			9		SD4	7	2	MEMR#
SD2	3	2	9	8		SD3	6	3	3MODE#
SA5	4	3	8	7		SA0	5	4	WRPRT#
	5	4	7	6		SA1
		5	6
		10P8R-8.2K					RN14	8P4R-47K
					SD5		8	1	CTSA#
	R380		8.2K				7	2	SINA
	R378		8.2K		SD6		6	3	DSRA#
	R379		8.2K		SD7		5	4	DCDA#

			+3VS
MEMW#		R373	10K(R)
R372	10K
SOUTA		R127	10K
XBUS RESET CONFIGURATION
DTRA		R122	10K(R)
BASE ADDRESS CONFIGURATION
DTRA# PULL-UP :4E
DTRA# PULL-DOWN :2E (DEFAULT)
RTSA#		R128	4.7K(R)

+3VS
R383	R377
10(R)	10K(R)

BID0

BID1

R374	R376
10K	10K

PCICLKIO

R382

10(R)

C521

10PF(R)

PLACE NEAR PC87393

LPC Super I/O (71-M4000-D03) B - 23