Clevo D410E manual Sheet 30 Mobility M9-P, AC/BE#0..3

Mobility M9-P

5,10

AAD[0..15]

BGA3A

AAD0

K28

AJ2

GPIO0

AAD28/VBCTL0

AD0

GPIO0

5,10

AAD28

AAD1

L29

Part 1 of 5

AK2

GPIO1

AAD29/VBCTL1

AAD2

L27

AD1

GPIO1

AK1

GPIO2

5,10

AAD29

AAD3

L30

AD2

GPIO2

AH3

GPIO3

+3VS

AAD4

L28

AD3

GPIO3

AH2

GPIO4

T377

AAD[0..15]

AAD5

M29

AD4

GPIO4

AJ1

GPIO5

5,10

AAD[0..15]

AAD6

M27

AD5

GPIO5

AF4

GPIO6

T378

AAD[19..26]

AAD7

M30

AD6

GPIO6

AH1

GPIO7

T380

GPIO0

R538

10K(R)

AGP 1X clock feedback

AAD8

N30

AD7

GPIO7

AG3

GPIO8

R539

10K(R)

5,10 AAD[19..26]

AAD9

N28

AD8

GPIO8

AF3

GPIO9

T381

GPIO1

R540

10K(R)

phase adjustment wrt

5

AC/BE#[0..3]

AC/BE#[0..3]

AAD10

P29

AD9

GPIO9

AG2

R541

10K

+3VS

R542

10K(R)

refclk(cpuclk)

AD10

GPIO10

GPIO11

SBA[0..7]

AAD11

P27

AD11

GPIO11

AF2

T382

AAD12

P30

AG1

5

SBA[0..7]

ST[0..2]

AAD13

P28

AD12

GPIO12

AF1

T383

5

ST[0..2]

AAD14

R29

AD13

GPIO13

AE2

T384R543

10K

AAD15

R27

AD14

GPIO14

AE1

R544

10K

GPIO2

R545

10K(R)

AAD16/VADE

U28

AD15

GPIO15

R547

10K(R)

Clock phase adjustment

AAD17/AVSYNC

U30

AD16

AE5

GPIO3

R549

10K(R)

5,10

AAD[19..26]

AAD18/AHSYNC

V27

AD17

ROMCS#

T385

R551

10K(R)

between x1clk and x2clk

AAD19

V29

AD18

/

AJ5

AAD20

V28

AD19

GPIO

ZV_LCDDATA0

AK5

GPIO9

R554

10K(R)

AAD21

V30

AD20

ZV_LCDDATA1

AG6

T388

R556

10K

Control ROM identifier

AAD22

W27

AD21

ZV_LCDDATA2

AH6

AAD23

W30

AD22

ZV_LCDDATA3

AJ6

AAD24

AA28

AD23

/

ZV_LCDDATA4

AK6

T391

AAD25

Y30

AD24

TMDS

ZV_LCDDATA5

AG7

AAD26

AA27

AD25

ZV_LCDDATA6

AH7

LCDID0

AAD27/VBDE

AA30

AD26

ZV_LCDDATA7

AJ7

R562

0

LCDID0

11,15

AAD28/VBCTL0

AB28

AD27

ZV_LCDDATA8

AK7

R564

0

LCDID1

MOBILITY

THE VALUES OF RSET AND R2SET SHOWN IN THE TABLE MAY BE

AAD29/VBCTL1

AA29

AD28

ZV_LCDDATA9

AG8

R566

0 LCDID2

LCDID1

11,15,27

AD29

ZV_LCDDATA10

LCDID2

11,15,27

APPROXIMATE VALUES ONLY (SUITABLE FOR PROTOTYPING)

AAD30/BHSYNC

AB27

AD30

/ EXT

ZV_LCDDATA11

AH8

RSET

715R

BEFORE GOING INTO PRODUCTION,CONTACT YOUR ATI

5

AC/BE#[0..3]

AAD31/BVSYNC

AB30

AJ8

+3VS

AD31

ZV_LCDDATA12

AK8

REPRESENTATIVE FOR THE RSET/R2SET VALUES QUALIFIED FOR

AC/BE#0

N27

ZV_LCDDATA13

AG9

T396

R570

R571

R2SET

715R

MASS PRODUCTION

AC/BE#1

R30

C/BE#0

ZV_LCDDATA14

AH9

AC/BE#2

U29

C/BE#1

ZVPORT ROM

ZV_LCDDATA15

AJ9

10K

10K

AC/BE#3

W28

C/BE#2

PCI/AGP

ZV_LCDDATA16

AK9

T399R574

I2CCLK

5

APAR

ASTOP#

T27

C/BE#3

ZV_LCDDATA17

AG10

33

PAR

ZV_LCDDATA23

AGPCLKATI

AG30

ZV_LCDDATA18

AH10

R575

33

I2CDATA

Close to Mobility M7-P

PCICLK

ZV_LCDDATA19

+3VS

9,10,13,14,20,22,24

PCIRST#

PCIRST#

AH30

RST#

ZV_LCDDATA20

AJ10

Y9

AREQ#

AF29

AK10

5

AREQ#

AGNT#

AF27

REQ#

ZV_LCDDATA21

AG11

T504

1

4

4

AGPCLKATI

5

AGNT#

APAR

R28

GNT#

ZV_LCDDATA22

AH11

5

ASTOP#

ADEVSEL#

T29

STOP#

AJ4

MHz

R576

5

ADEVSEL#

ATRDY#

T28

DEVSEL#

ZV_LCDCNTL0

AK4

T404

2

3

10

5

ATRDY#

AIRDY#

T30

TRDY#

ZV_LCDCNTL1

AH5

T405

27.0000MHZ-OSC

C693

5

AIRDY#

INTA#

AFRAME#

U27

IRDY#

ZV_LCDCNTL2

AG5

0.01U

5

AFRAME#

R577

0

AH29

FRAME#

ZV_LCDCNTL3

T503

XTALIN

9,10,13

INTA#

INTD#

R578

0(R)

INTA#

LDC0-

13,25

INTD#

WBF#

R579

33

AE27

AK16

5

WBF#

WBF/SERR#

TXOUT_L0N

AJ16

LDC0+

LDC0-

10,11

R594

C689

R580

100K

STP_AGP#

AG29

TXOUT_L0P

AK17

LDC1-

LDC0+

10,11

10P

+3V

R581

100K

AGP_BUSY#

AG28

STP_AGP#

TXOUT_L1N

AJ17

LDC1+

LDC1-

10,11

OSC1.8

AD_STB0

RBF#

AE30

AGP_BUSY#

TXOUT_L1P

AK18

LDC2-

LDC1+

10,11

120

5

RBF#

R582

0

N29

RBF#

TXOUT_L2N

AJ18

LDC2+

LDC2-

10,11

5

AD_STB0

AD_STB1

R583

0

W29

AD_STB0

TXOUT_L2P

AK20

LDC3-

LDC2+

10,11

R597

5

AD_STB1

SB_STB

R584

0

AC29

AD_STB1

LVDS

TXOUT_L3N

AJ20

LDC3+

LDC3-

10,11

5

SB_STB

SB_STB

TXOUT_L3P

AK19

LL1C-

LDC3+

10,11

SBA0

AD29

TXCLK_LN

AJ19

LL1C+

LL1C-

10,11

150

5

SBA[0..7]

SBA1

AE28

SBA0

TXCLK_LP

AH18

LDC4-

LL1C+

10,11

+3VS

Close to Mobilty M9-P

SBA2

AD30

SBA1

M9-P

AGP2X

TXOUT_U0N

AG18

LDC4+

LDC4-

10,11

ENABKL

SBA7

AC28

SBA6

TXOUT_U2P

AH22

LDC7-

LDC6+

10,11

SBA3

AD27

SBA2

TXOUT_U0P

AH19

LDC5-

LDC4+

10,11

SBA4

AC30

SBA3

TXOUT_U1N

AG19

LDC5+

LDC5-

10,11

+3V

R589

SBA5

AC27

SBA4

TXOUT_U1P

AH20

LDC6-

LDC5+

10,11

1K

SBA6

AB29

SBA5

TXOUT_U2N

AG20

LDC6+

LDC6-

10,11

ATI_AGP1.5/3.3

5

ST[0..2]

SBA7

TXOUT_U3N

AG22

LDC7+

LDC7-

10,11

R591

ENABKL

10,11

ST0

AF30

TXOUT_U3P

AH21

LL2C-

LDC7+

10,11

100K

D

ST1

AF28

ST0

TXCLK_UN

AG21

LL2C+

LL2C-

10,11

Q29

C690

ST2

AE29

ST1

TXCLK_UP

LL2C+

10,11

BLON#

G

S

ST2

AE13

ENAVDD

SB_STB#

DIGON

ENAVDD

10,11

2N7002

0.1U

R585

5

SB_STB#

R586

0

AD28

AF13

BLON#

910_1%

AD_STB#0

R587

0

M28

SB_STB#

AGP4X

TMDS

BLON#

AK12

CLKOUT

VDDREF

+1.8V

5

AD_STB#0

AD_STB#1

R588

0

AK24

ADSTB0#

TXCM

Y29

5

AD_STB#1

ADSTB1#

TX0M

AJ13

T407

AGPREF

K30

AGPREF

AK13

K29

AGPTEST

TX1M

AJ14

R634

8.2K(R)

Z1198 R635

8.2K(R)

Z11100

TX1P

AK14

R590

C692

AJ15

U39

C691

R592

R593

715

AJ24

TX2M

1K_1%

R2SET

TX2P

AK15

0.1U

10U(0805)

47_1%

AJ12

MCLK_SREADR636

22(R)

8

16

AK23

C_R

TXCP

T414

15

VDDO1

6

L109

0(R)

+3V

AK22

Y_G

DAC2

DVIDDCCLK

AF12

OSC1.8

R637

22(R)

14

VDD

5

Z11102

R638

10(R)

AG24

COMP_B

AE12

VDDO0

VDDA

10

C

C

AG25

H2SYNC

DVIDDCDATA

I2CCLK

11

SCLK

PD#

12

C698

C699

C701

C700

Y

T418

V2SYNC

AF11

I2CDATA

10

13

10

Y

COMPOSITE

AH25

CRT2DDCCLK

HPD

R595

100k

SDATA

REF_STOP

0.1U(R)

10U(0805)(R)

10

COMPOSITE

T419

AH26

XTALIN

2

X1

GND

1

0.1U(R)

10U(0805)(R)

CRT2DDCDATA

T420

SUS_STAT#

AJ28

R596

10K +3VS

T488

3

7

SSC

DAC1

Z11103

X2

GND

T421

AJ26

AH24

R598

1K

9

SS_ENA

GNDA

4

SSIN

TESTEN

T422

AJ25

VGADDCCLK VGADDCDATA

R639

8.2K(R)

ICS91719(R)

5 AAD30/BHSYNC

AAD30/BHSYNC

XTALIN

SSOUT

AUXWIN

RSET

VSYNC HSYNC B G R

R599

0(R)

AJ29

XTALIN

OSC1.8

R600

0

T423

AJ30

XTALOUT

AJ27

AH27 AH28

AK25

AG27 AG26 AK26 AK27 AK28

5 AAD31/BVSYNC

AAD31/BVSYNC

5 AAD18/AHSYNC

AAD18/AHSYNC

AAD17/AVSYNC

R

9

MCLK_SREAD

R601

0(R)

5 AAD17/AVSYNC

31 MCLK_SREAD

G

9

5,10

AAD16

AAD16/VADE

+3VS

R602

10K

B

9

HSY

9

5,10

AAD27

AAD27/VBDE

9

VGADDCCLK

R603

499

VSY

9

9

VGADDCDATA

Schematic Diagrams

Sheet 30 of 41

Mobility M9-P

B.Schematic Diagrams

Mobility M9-P (71-M4000-D03) B - 31