Pinout Specifications | Intel Itanium 2 Processor specs

Pinout Specifications

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Datasheet

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Intel Itanium 2 Processor manual Pinout Specifications

Contents

Datasheet Intel Itanium 2 Processor Datasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR# 106 Revision History Revision No Description Date Product Features Intel Itanium 2 Processor Datasheet Overview Processor Abstraction Layer State of Data Mixing Processors of Different Frequencies and Cache SizesTerminology Reference Documents Title Document Number Introduction System Bus Signals System Bus Power PinsSignal Groups Itanium 2 Processor System Bus Group Name Signals Signal DescriptionsItanium 2 Processor System Bus Signal Groups Symbol Parameter Core Minimum Typ Maximum Unit Package SpecificationsItanium 2 Processor Package Specifications Signal Specifications Itanium 2 Processor Power Supply SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum Unit AGTL+ Signals DC Specifications Sheet 2 Power Good Signal DC SpecificationsSystem Bus Clock Differential Hstl DC Specifications TAP Connection DC Specifications SMBus DC Specifications Lvttl Signal DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum Unit 11. SMBus AC Specifications Minimum Typ Maximum Maximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1 Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2 Overshoot/Undershoot Pulse Duration Activity Factor Reading Overshoot/Undershoot Specification Tables Vcterm Parameter Description Specification Units Absolute Pulse Duration nsOver AF = 1 Shoot 0143 Wired-OR Signals 0513 Power Pod Connector Signals 22. Itanium 2 Processor Power Pod Connector SignalsGroup Name Signals Power Pod Connector Absolute 23. Processor Core Voltage Identification Code1 VID2 VID1 VID0 State Transition Ramp Rate Comment 24. Processor Power StatesItanium 2 Processor System Bus Clock and Processor Clocking 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17# System Bus Reset and Configuration Timings for Cold Reset Recommended Connections for Unused Pins 26. Connection for Unused Pins Sheet 1Pins/Pin Groups Recommended TAP Signals 26. Connection for Unused Pins Sheet 2 System Management SignalsLvttl Power Pod Signals Reserved Pins Pinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal Name Pin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/Output Pin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 Location Pin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor Package Processor Substrate Units Itanium 2 Processor Package Power Tab Processor Bottom-Side Marking Package MarkingProcessor Top-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal Alert Case Temperature Case Temperature SpecificationSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal Management Itanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signals System Management Interface Signal DescriptionsSignal Name Pin Count Description System Management Bus System Management Feature Specifications SMBus Device Addressing 9Xh Processor Information ROM Format Sheet 1 Processor Information ROMEeprom SMBus Addressing on the Itanium 2 Processor Cache Processor Information ROM Format Sheet 2Offset Function Examples Section Bits Features Processor Information ROM Format Sheet 3Offset Function Examples Section Bits Package Part Numbers Other Scratch EepromProcessor Information ROM Format Sheet 4 Thermal Sensing Device Current Address Read SMBus PacketRandom Address Read SMBus Packet Byte Write SMBus Packet Thermal Sensing Device Supported SMBus Transactions 13. Command Byte Bit Assignment Register Command Reset State FunctionThermal Sensing Device Registers Thermal Reference Registers Configuration Register 15. Thermal Sensing Device Configuration RegisterThermal Limit Registers Status Register 16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate HzConversion Rate Register Alphabetical Signals Reference Table A-2. Effective Memory Type Signal Encoding ATTR30# I/OBCLKp/BCLKn 8 BE70# I/O BERR# I/O Table A-3. Special Transaction Encoding on Byte EnablesSpecial Transaction Byte Enables70# BINIT# I/O 11 BNR# I/O12 BPM50# I/O BPRI# Table A-6. BR30# Signals and Agent IDs Bus Signal Agent 0 Pins Agent 3 PinsBREQ30# I/O Pin Sampled CCL# I/O D1270# I/O# I/O DBSYC1# O DBSYC2# O DEFER#24 DEN# I/O 25 DEP150# I/O 27 DPS# I/O DRDY# I/ODRDYC1# O DRDYC2# O 33 FCL# I/O FERR# OHIT# I/O and HITM# I/O ID90# IP10# LEN20# I/OTable A-9. Length of Data Transfers LEN20# LINT10 OWN# I/OPMI# REQ50# I/O Transaction REQa50# REQb50# RESET#52 RP# I/O RS20# RSP#SBSYC1# O SBSYC2# O STBn70# and STBp70# I/O TDO OTHRMTRIP# O Table A-11. STBp70# and STBn70# Associations Signal Summaries Table A-12. Output Signals Sheet 1Name Active Level Clock Signal Group TND# I/O Name Active Level Clock Signal Group Qualified Table A-12. Output Signals Sheet 2Table A-13. Input Signals Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver 108