Intel Itanium 2 Processor specification

Thermal Specifications

Figure 5-2. Itanium® 2 Processor Package Thermocouple Location

24.13
45.00	Thermocouple Location

All dimensions are measured in mm. Not to scale.

001103a

Datasheet

77

Image 77

Intel manual Itanium 2 Processor Package Thermocouple Location

Contents

Intel Itanium 2 Processor Datasheet Datasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures BINIT#, HIT#, HITM#, BNR#, TND#, BERR# Tables 106 Revision No Description Date Revision History Intel Itanium 2 Processor Product Features Datasheet Processor Abstraction Layer Overview State of Data Mixing Processors of Different Frequencies and Cache SizesTerminology Title Document Number Reference Documents Introduction System Bus Power Pins System Bus SignalsSignal Groups Itanium 2 Processor System Bus Group Name Signals Signal DescriptionsItanium 2 Processor System Bus Signal Groups Symbol Parameter Core Minimum Typ Maximum Unit Package SpecificationsItanium 2 Processor Package Specifications Itanium 2 Processor Power Supply Specifications Signal SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum Unit Power Good Signal DC Specifications AGTL+ Signals DC Specifications Sheet 2System Bus Clock Differential Hstl DC Specifications TAP Connection DC Specifications Lvttl Signal DC Specifications SMBus DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum Unit Minimum Typ Maximum 11. SMBus AC Specifications 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1 Maximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2 Overshoot/Undershoot Magnitude Activity Factor Overshoot/Undershoot Pulse Duration Vcterm Reading Overshoot/Undershoot Specification Tables Absolute Pulse Duration ns Parameter Description Specification UnitsOver AF = 1 Shoot 0143 Wired-OR Signals 0513 22. Itanium 2 Processor Power Pod Connector Signals Power Pod Connector SignalsGroup Name Signals Power Pod Connector Absolute VID2 VID1 VID0 23. Processor Core Voltage Identification Code1 State Transition Ramp Rate Comment 24. Processor Power StatesItanium 2 Processor System Bus Clock and Processor Clocking Ratio of Bus Frequency A21# A20# A19# A18# A17# 25. Itanium 2 Processor System Bus Ratios System Bus Reset and Configuration Timings for Cold Reset 26. Connection for Unused Pins Sheet 1 Recommended Connections for Unused PinsPins/Pin Groups Recommended TAP Signals System Management Signals 26. Connection for Unused Pins Sheet 2Lvttl Power Pod Signals Reserved Pins Pinout Specifications Pin Name System Bus Input/Output Signal Name Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Pin/Signal Information Sorted by Pin Name Sheet 2 Pin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Location Pin/Signal Information Sorted by Pin Location Sheet 1 Pin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Itanium 2 Processor Package Mechanical Dimensions Substrate Units Processor Itanium 2 Processor Package Power Tab Processor Bottom-Side Marking Package MarkingProcessor Top-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Alert Thermal Features Case Temperature Specification Case TemperatureSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal Management Itanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signal Descriptions System Management Interface SignalsSignal Name Pin Count Description System Management Bus System Management Feature Specifications 9Xh SMBus Device Addressing Processor Information ROM Format Sheet 1 Processor Information ROMEeprom SMBus Addressing on the Itanium 2 Processor Cache Processor Information ROM Format Sheet 2Offset Function Examples Section Bits Processor Information ROM Format Sheet 3 FeaturesOffset Function Examples Section Bits Package Part Numbers Other Scratch EepromProcessor Information ROM Format Sheet 4 Current Address Read SMBus Packet Thermal Sensing DeviceRandom Address Read SMBus Packet Byte Write SMBus Packet Thermal Sensing Device Supported SMBus Transactions Register Command Reset State Function 13. Command Byte Bit AssignmentThermal Sensing Device Registers Thermal Reference Registers 15. Thermal Sensing Device Configuration Register Configuration RegisterThermal Limit Registers Status Register 16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate HzConversion Rate Register Alphabetical Signals Reference ATTR30# I/O Table A-2. Effective Memory Type Signal EncodingBCLKp/BCLKn 8 BE70# I/O BERR# I/O Table A-3. Special Transaction Encoding on Byte EnablesSpecial Transaction Byte Enables70# 11 BNR# I/O BINIT# I/O12 BPM50# I/O BPRI# Bus Signal Agent 0 Pins Agent 3 Pins Table A-6. BR30# Signals and Agent IDsBREQ30# I/O Pin Sampled D1270# I/O CCL# I/O# I/O DBSYC1# O DEFER# DBSYC2# O24 DEN# I/O 25 DEP150# I/O DRDY# I/O 27 DPS# I/ODRDYC1# O DRDYC2# O FERR# O 33 FCL# I/OHIT# I/O and HITM# I/O ID90# LEN20# I/O IP10#Table A-9. Length of Data Transfers LEN20# OWN# I/O LINT10PMI# REQ50# I/O Transaction REQa50# REQb50# RESET#52 RP# I/O RSP# RS20#SBSYC1# O SBSYC2# O TDO O STBn70# and STBp70# I/OTHRMTRIP# O Table A-11. STBp70# and STBn70# Associations Table A-12. Output Signals Sheet 1 Signal SummariesName Active Level Clock Signal Group TND# I/O Name Active Level Clock Signal Group Qualified Table A-12. Output Signals Sheet 2Table A-13. Input Signals Table A-15. Input/Output Signals Multiple Driver Table A-14. Input/Output Signals Single Driver 108