System Management Feature Specifications

Figure 6-1. Logical Schematic of SMBus Circuitry

 

 

 

 

 

 

3.3V

 

 

 

Intel® Itanium® 2 Processor

 

 

 

 

 

 

Core

 

 

 

 

 

 

 

 

10K

 

10K

10K

 

 

THERMDA

 

 

 

 

 

 

A0

VCC

 

 

 

 

THERMDC

 

 

 

 

 

 

 

 

A1

Processor

SC

 

 

 

 

 

A2

Information

SD

 

 

 

 

 

 

ROM

 

 

VCC

 

STBY

 

 

 

 

 

 

 

 

 

 

 

A0

Thermal

SC

 

 

 

 

 

 

 

 

 

 

 

 

A1

Sensing

SD

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

10K

 

 

ALERT

 

 

 

VCC

 

 

 

 

 

A0

SC

 

 

 

 

 

 

 

 

 

 

 

A1

Scratch

SD

 

 

 

 

 

10K

 

 

 

 

 

 

EEPROM

 

 

 

 

 

 

A2

WP

 

 

 

 

 

10K

 

 

 

 

 

 

 

SMA0

 

SMWP

 

 

 

 

 

SMA1

 

SMSD

 

 

 

3.3V

SMA2

 

 

SMSC

THRMALERT#

 

3.3V

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

10K

 

 

Stuffing

 

 

 

 

 

 

 

Options

 

 

 

 

 

System Board

System Board

NOTE:

1.Actual implementation may vary.

2.For use in general understanding of the architecture.

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Datasheet

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Intel Itanium 2 Processor manual System Management Feature Specifications