Intel Itanium 2 Processor manual LINT10, Own# I/O, Pmi#, REQ50# I/O

Signals Reference

A.1.44 LINT[1:0] (I)

LINT[1:0] are local interrupt signals. These pins are disabled after RESET#. LINT[0] is typically software configured as INT, an 8259-compatible maskable interrupt request signal. LINT[1] is typically software configured as NMI, a non-maskable interrupt.Both signals are asynchronous inputs.

A.1.45	LOCK# (I/O)
	LOCK# is never asserted or sampled in the Itanium 2 processor system environment.
A.1.46	NMI (I)
	The NMI signal is the Non-maskable Interrupt signal. Asserting NMI causes an interrupt with an
	internally supplied vector value of 2. An external interrupt-acknowledge transaction is not
	generated. If NMI is asserted during the execution of an NMI service routine, it remains pending
	and is recognized after the EOI is executed by the NMI service routine. At most, one assertion of
	NMI is held pending.
	NMI is rising-edge sensitive. Recognition of NMI is guaranteed in a specific clock if it is asserted
	synchronously and meets the setup and hold times. If asserted asynchronously, asserted and
	deasserted pulse widths of NMI must be a minimum of two clocks.This signal must be software
	configured to be used either as NMI or as another local interrupt (LINT1 pin).
A.1.47	OWN# (I/O)
	The Guaranteed Cache Line Ownership (OWN#) signal is driven to the bus on the second clock of
	the Request Phase on the Ab[5]# pin. OWN# is asserted if cache line ownership is guaranteed. This
	allows a memory controller to ignore memory updates due to implicit writebacks.
A.1.48	PMI# (I)
	The Platform Management Interrupt (PMI#) signal triggers the highest priority interrupt to the
	processor. PMI# is usually used by the system to trigger system events that will be handled by
	platform specific firmware.
A.1.49	PWRGOOD (I)
	The Power Good (PWRGOOD) signal must be deasserted (L) during power-on, and must be
	asserted (H) after RESET# is first asserted by the system.
A.1.50	REQ[5:0]# (I/O)
	The REQ[5:0]# are the Request Command signals. They are asserted by the current bus owner in
	both clocks of the Request Phase. In the first clock, the REQa[5:0]# signals define the transaction

type to a level of detail that is sufficient to begin a snoop request. In the second clock, REQb[5:0]# signals carry additional information to define the complete transaction type. REQb[4:3]# signals transmit DSZ[1:0]# or the data transfer information of the requestor for transactions that involve data transfer. REQb[2:0]# signals transmit LEN[2:0]# (the data transfer length information). In both clocks, REQ[5:0]# and ADS# are protected by parity RP#.

Datasheet 101