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Intel Itanium 2 Processor Mechanical Specifications Figure 4-3. Itanium 2 Processor Package Power Tab

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Datasheet 71

Mechanical SpecificationsFigure 4-3. Itanium® 2 Processor Package Power Tab

All dimensions are measured in mm. Not to scale. 001159a

Top View

Bottom View

46.96

42.21

46.00

2x 9.10 2x 12.91

4x R1.00

C

L

2.98

12x 2.92 2x 25.85

C

L

12x 38.76

90.00

45.0042.46

2x R1.20

46.74 48.26

24.13

10x 1.15

12x 0.86

2x 16.10

2.48

46.96 C

L

Contents

Main Intel Itanium 2 Processor Datasheet February 2006 Page Contents Page Figures Tables Page Revision History Intel Itanium 2 Processor Product Features Page 1 1.1 Overview 1.2 Processor Abstraction Layer 1.3 Mixing Processors of Different Frequencies and Cache Sizes 1.4 Terminology 1.5 State of Data Introduction 1.6 Reference Documents Page 2 2.1 Itanium 2 Processor System Bus 2.1.1 System Bus Power Pins 2.1.2 System Bus No Connect 2.2 System Bus Signals 2.2.2 Signal Descriptions 2.3 Package Specifications 2.4 Signal Specifications Table 2-3. Itanium 2 Processor Power Supply Specifications Table 2-4. AGTL+ Signals DC Specifications (Sheet 1 of 2) Table 2-5. Power Good Signal DC Specifications Table 2-6. System Bus Clock Differential HSTL DC Specifications Table 2-7. TAP Connection DC Specifications Table 2-4. AGTL+ Signals DC Specifications (Sheet 2 of 2) Table 2-8. SMBus DC Specifications Table 2-9. LVTTL Signal DC Specifications Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 1 of 2) Table 2-11. SMBus AC Specifications Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2) 2.4.1 Maximum Ratings Figure 2-1. Generic Clock Waveform 90% Vcc V (3.3V) T SMSC 2.5 System Bus Signal Quality Specifications and Measurement Guidelines 2.5.1 Overshoot/Undershoot Magnitude 2.5.2 Overshoot/Undershoot Pulse Duration 2.5.3 Activity Factor 2.5.4 Reading Overshoot/Undershoot Specification Tables 2.5.5 Determining if a System Meets the Overshoot/Undershoot Specifications Page Page 2.5.6 Wired-OR Signals Page 2.6 Power Pod Connector Signals Page 2.7 Itanium 2 Processor System Bus Clock and Processor Clocking Page Page 2.8 Recommended Connections for Unused Pins Figure 2-7. System Bus Reset and Configuration Timings for Warm Reset t -2 t -1 t TC= Bus ratio signals must be asserted no later than RESET# T Table 2-26. Connection for Unused Pins (Sheet 2 of 2) 3 000638b Page Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 2 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 3 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 4 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 5 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 6 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 7 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 8 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 9 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 10 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 11 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 12 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 13 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 14 of 15) Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 15 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 1 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 2 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 3 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 4 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 5 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 6 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 7 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 8 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 9 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 10 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 11 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 12 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 13 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 14 of 15) Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 15 of 15) Page 4 4.1 Mechanical Dimensions Mechanical Specifications NOTE: Figure 4-2. Itanium 2 Processor Package Processor IHS Height Substrate Height Units Mechanical Specifications Figure 4-3. Itanium 2 Processor Package Power Tab 4.2 Package Marking 4.2.1 Processor Top-Side Marking 4.2.2 Processor Bottom-Side Marking Page Page 5 5.1 Thermal Features 5.1.1 Thermal Alert 5.1.2 Enhanced Thermal Management 5.1.3 Thermal Trip 5.2 Case Temperature Page Page 6 Specifications 6.1 System Management Bus 6.1.1 System Management Bus Interface 6.1.2 System Management Interface Signals Figure 6-1. Logical Schematic of SMBus Circuitry NOTE: 1.Actual implementation may vary. 2.For use in general understanding of the architecture. Core System Board 6.1.3 SMBus Device Addressing 6.2 Processor Information ROM Table 6-3. EEPROM SMBus Addressing on the Itanium 2 Processor Table 6-4. Processor Information ROM Format (Sheet 1 of 4) Table 6-4. Processor Information ROM Format (Sheet 2 of 4) Table 6-4. Processor Information ROM Format (Sheet 3 of 4) 6.3 Scratch EEPROM 6.4 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions 6.5 Thermal Sensing Device 6.6 Thermal Sensing Device Supported SMBus Transactions 6.7 Thermal Sensing Device Registers 6.7.1 Thermal Reference Registers 6.7.2 Thermal Limit Registers 6.7.3 Status Register 6.7.4 Configuration Register 6.7.5 Conversion Rate Register A Signals Reference A.1 Alphabetical Signals Reference A.1.1 A[49:3]# (I/O) A.1.2 A20M# (I) A.1.3 ADS# (I/O) A.1.6 ATTR[3:0]# (I/O) A.1.7 BCLKp/BCLKn (I) A.1.8 BE[7:0]# (I/O) A.1.9 BERR# (I/O) A.1.10 BINIT# (I/O) A.1.11 BNR# (I/O) A.1.12 BPM[5:0]# (I/O) A.1.13 BPRI# (I) A.1.14 BR[0]# (I/O) and BR[3:1]# (I) A.1.15 BREQ[3:0]# (I/O) Page A.1.22 DBSY_C2# (O) A.1.23 DEFER# (I) A.1.24 DEN# (I/O) A.1.25 DEP[15:0]# (I/O) A.1.26 DHIT# (I) Page Page A.1.39 IGNNE# (I) A.1.40 INIT# (I) A.1.41 INT (I) A.1.42 IP[1:0]# (I) A.1.43 LEN[2:0]# (I/O) Page A.1.51 RESET# (I) A.1.52 RP# (I/O) Page A.1.59 STBn[7:0]# and STBp[7:0]# (I/O) A.1.60 TCK (I) A.1.61 TDI (I) A.1.62 TDO (O) A.1.63 THRMTRIP# (O) A.2 Signal Summaries Signals Reference Table A-13. Input Signals Table A-12. Output Signals (Sheet 2 of 2) Signals Reference Table A-14. Input/Output Signals (Single Driver) Table A-15. Input/Output Signals (Multiple Driver)