Electrical Specifications
Figure 2-7. System Bus Reset and Configuration Timings for Warm Reset
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BCLK |
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PWRGOOD |
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| TA |
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RESET# |
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TC | TB |
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Bus Ratio |
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(A[21:17]#) |
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Additional |
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| TE |
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Configuration |
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Signals |
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TA = 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
TB = 1 ms minimum for warm reset
TC = Bus ratio signals must be asserted no later than RESET#
TD = 2 BCLKs minimum, 3 BCLKs maximum
TE = 4 BCLKs minimum
TF = 2 BCLKs minimum, 3 BCLKs maximum
000777b
2.8Recommended Connections for Unused Pins
Pins that are unused in an application environment (as opposed to testing environment) should be connected to the states listed in Table
Table 2-26. Connection for Unused Pins (Sheet 1 of 2)
Pins/Pin Groups | Recommended | Notes | |
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AGTL+ pins | H | 1, 2 | |
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HSTL Clock Signals | Must be used |
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All Power Signals | Must be used |
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PWRGOOD | Must be used |
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TUNER[2:1] | Must be used |
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TAP Signals |
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TCK | L | 1, 3 | |
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TRST# | L | 1, 3 | |
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TDI | H | 1, 3 | |
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TDO | H | 1, 3 | |
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TMS | H | 1, 3 | |
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Datasheet | 35 |