Schematic Diagrams
Clock Generator B - 3
B.Schematic Diagrams
Clock Generator
REF _ 1 4 .31 8 M
C441
1U_6.3V_04
PM_STPPCI#24
3.3VS
CLK_MINI_3G
RN 3 3
4P2R X33_04
14
23
0
D03-0221
166 MHz
3.3VM_CLK
CLKDREFSS
C4 40
1U _6 . 3 V _ 04
C4 59
*.1U_10V_X7R _04
C439
*.1U_10V_X7R_04
Layout note:
CL K_D RE F# 7
C LK_BSEL1
R 215 10K_04
CL K_P CIE_ MINI 26
FSLC
CLK_GLAN
Insatlled: Differential clock
le vel is high er
PCLK_ICH23
R4 9 4 *0 _0 4
1
CLK_PCIE_3GPLL
RN 3 4
4P2R X33_04
14
23
CL K_D RE F 7
CLKDREF
R509 33_04
R2 1 0
1K_04
PER EQ 1#: PCIECLK 0, 6
PER EQ 2#: PCIECLK 1, 8
PER EQ 3#: PCIECLK 2, 4
P ER EQ 4#: P CI ECL K 3, 5, 7
PER EQ [1. .4]# have
internal pull up
D03-0221
CLK_MCH_BCLK
VTT_ PW R_GD
RN 3 2
4P2R X33_04_-U
14
23
FS B
R205 *0_04
CLK_P CIE_CARD READ ER 2 9
FS A
3.3VS 3,6,7,10,12,13,14,15,22,23,24,25,26,27,28,29,30,31,32,33,34,35,39,41,43
CLK_P CIE_GLAN 31
C LKSAT A#
C LK_ NEW _ C ARD#
1
M CH_ BSEL 2 7
CLK_D REFSS 7
CLK_M CH _BC LK # 5
3. 3 V M _ C LK
IC H_ SMBC LK012,13,24
CLK_CPU_BCLK
PCLKKBC
C728
22P_50V_04
C4 3 0
*.1U_10V _X7R_04
30mils
IC H_ SMBD AT012,13,24
CL K_S ATA 2 2
VGA_ PEXCL K#
1.0 5 VS 3 ,4,5 ,7 ,9,1 0 ,2 2,2 5 , 37 ,3 9
CLK_MINI_3G#
CK 50 5
R 2 19 10 0 K _ 04
C743 *10P_50V_04
CLK_D REFSS# 7
C4 61
.1U _10V_X7R_04
C4 7 2
*.1U_10V_X7R _04
IC SPCIC LK1
FSLA
F re que nc y
CLK_DREF#
1.05VS
CL K_P CIE_ MINI_ 3 G 2 7
C LKM CH_ BC LK
R 211 0_04
R208 10K_04
CL K_C PU_ BCL K 3
C PU_BSEL 23
U2 4
ICS9LPR363DG LF
5
11
56
62
49
51
35
48
52
2
6
8
55 16
61
12
42
34
58
57
45
36
33
60
3
4
28
50
54
9
64
13
21
37
53
32
30
31
27
26
24
25
23
22
19
20
18
17
14
15
10
47
7
1
29
46
39
38
41
40
44
43
59
63
PCIC LK3 /* SELPC IEX0_ L CD#
VDD 48
VD DREF
CPU _S T O P#
CPUT _ L1 F
CPU C_L0
PCIeC_L5
CPU C_L1F
CPUT_L0
GND
GN D
PCIC LK_ F 4 /IT P_EN
SDATA FSL B/TEST_MO DE
REF 1 /F SL C/T ES T_S EL
FSLA/USB_48M Hz
VDDP CIEX
*PWRSAVE #
X1
X2
VDD A
PC IeT_L5
*PEREQ 4#
REF0_14.318M
PCIC LK1
PCIC LK2
VD DPC IEX
VD DCPU
SCLK
*SELLCD _27#/PC ICLK_F5
** PCICLK0 /REQ _SE L
GND
VDD PCIEX
GN D
GND
*PEREQ 3#
PC IeT_L4
PCIeC_L4
SATACLKC_L
SATACL KT_ L
PC IeT_L3
PCIeC_L3
PCIeC_L2
PC IeT_L2
PC IeT_L1
PCIeC_L1
27 SS /L CD _SS C GC /PCIe C_ L 0
27FIX/ LC D_SSCG T/PC IeT_L0
PC IeT _ L9 /DO TT_ 9 6M Hz L
PCIeC_L9/D OTC_96M HzL
VTT_ PW R _G D/PD#
VREF
VDD PCI
VD DPC I
GND
GN DA
PC IeT_L6
PCIeC_L6
PCIeT_L7/PEREQ 1#
PC IeC _L7/PEREQ 2#
PCIe T _L 8 /CP U ITP T_ L 2
P CIe C_ L8 /C P UITP C_ L 2
GND
PCI/PC IEX_STOP#
R 199 300_1% _04
PC LK _KBC34
CLK_MINI#
1
C PU_ BSEL 13
CLK_PCIE_GLAN
C LK_SAT A
Place terminationclose to
ICS9LPR363
CL K_C PU_ BCL K # 3
CLK_ICH
RN 3 1
4P2R X33_04_-U
14
23
R203 475_1%_04
CLK_ BSEL 0
CLK_CARDREADER
RN 2 8
4P2R X33_04
1 4
2 3
PW RSAVE# 2 4
CL K_S ATA# 2 2
CL K_ ICH 48
R495
1K_04
R 213 2.2K_04
M CH_ BSEL 0 7
Layout note:
1.05VS
CLK_MINI
VG APEXC LK
1.05VS
RN 3 6
4P2R X33_04
14
23
0
C LK_PC IE_MINI_3G#
R 2 0 7 1K _0 4
CL K_ ICH 14
C431
.1U _10V_X7R_04
C442
.1 U_ 16 V _ 0 4
NEW C ARD_ CL K R EQ# 26
C LK_PC IE_NEW _ CAR D
RN 3 5
4P2R X33_04
14
23
CL K_ ICH1 424
XTAL _ OU T
R214
*56_04
D03B-0329
R200
1K_1%_04
200 MHz
CL K_P CIE_ 3G PL L# 7
C473 *10P_50V_04
1
PCLKICH
CLK_ BSEL2
106 6 MHz
CL K_ P CIE_ ICH 2 3
C7 29
22 P _ 50 V _ 0 4
MC H_ BSEL1 7
WLAN _CLKREQ# 26,27
VGA_ PEXCL K 15
CLK_CPU_BCLK#
RN 2 9
4P2R X33_04
1 4
2 3
C460
.1U_10V_X7R_04
3. 3 V S
D03B-0329
CLK_ BSEL 2
800 M Hz
BSE L1
CL K_P CIE_ 3G PL L 7
C LK_SAT A#
CLK_ICH#
C741
10U _10V_08
CL K_ PCIE _ ICH # 23
CLK_MCH_BCLK#
CLK_PCIE_CARDREADER
R 606 10K_04
VGA_ PEXCL K# 1 5
CL K_ B SEL 1
RN 2 7
4P2R X33_04
1 4
2 3
R2 20 0 _0 4
R 498 10K_04
RN 3 0
4P2R X33_04
1 4
2 3
D03B-0329
CLK_DREFSS#
VGA_ PEXCL K
20mils
CL K_ ICH4 8
CL K_ ICH1 4
CLK_GLAN#
PLA CE CRYS TAL WIT HIN 500
MILS OF ICS9LPR363
40mils
CLK_P CIE_CARD READ ER# 29
CLK_PCIE_ICH#
D03B-0329
C LK_PC IE_MINI_3G
R221 33_04
C LK_PC IE_NEW _ CAR D#
RN 7
4P2R X33_04
14
23
.
L29
HC B1608KF-121T25_06
266 MHz
3.3VM_CLK
533 M Hz
PCLK_ KBC
PCLK_ ICH
C471 *10P_50V_04
CL K_ ICH4 824
C432 *10P_50V_04
CLK_PWRGD24
RN 8
*4P2RX33_04_+U
14
23
R 4 99 3 3 _0 4
X2
14.318M Hz
12
EMI
MC H _ CL K RE Q# 7
CLK_3GPLL
R206
1K_04
0
D03-0221
CLK_DREF
C LKSAT A
667 M Hz
R6 07 *0 _ 0 4_ + H
R496
1K_04
XTAL _ IN
CLK_CARDREADER#
ICSR EQ_ SEL
R 2 12 3 3 _0 4
C PU_BSEL 03
C L K_PC IE_ MINI
3.3V M_CLK
CLK_P CIE_NEW_CAR D# 26
0
CLK_PCIE_ICH
R209 *475_1% _04
133 MHz
C462
1U_6.3V_04
CLKDREF#
CLK_NEW_CARD
FS C
D03-0221
CLK_DREFSS
CLOCK GENERATOR
CL K_P CIE_ MINI_3 G# 2 7
ICSP C ICL K_ F 4
Ho st Cl oc k
CLK_M CH _BC LK 5
CLK_PCIE_GLAN#
CLK_P CIE_NEW_CAR D 26
C LK_3GPLL#
3. 3 V S
C736
*10U_10V_08
R2 0 4
1K_04
Layout note:
PCLK_ KBC
CLKCPU_BCLK
C LKM CH_ BC LK#
C738
1 0U _ 10 V _ 08
CLK_P CIE_GLAN# 31
CLK_PCIE_3GPLL#
RN 3 7
4P2R X33_04
14
23
PER EQ3 #
IC SVREF
VG APEXC LK #
0
R497 *10K_04
CLK_PCIE_CARDREADER#
PM _ST PC PU#24
CLKCPU_BCLK#
FSLB
CLKDREFSS#
C L K_PC IE_ MINI#
0
D03-0221
BS EL 0
0
BS EL 2
dGPU_RUNPWROK24
CL K_P CIE_ MINI# 2 6
PCLKT PM
C LK_BSEL 0
0