Clevo M740TU, M760T, M760TU Penryn (Socket-P) CPU 1/2

Schematic Diagrams

B - 4 Penryn (Socket-P) CPU 1/2

B.Schematic Diagrams

Penryn (Socket-P) CPU 1/2

Sheet 3 of 51

Penryn (Socket-P)

CPU 1/2

COM P0

H_D#50

SMC_CPU_THERM 34

H_DSTBP#2 5

H_D#7

H_ A# 2 1

H_D#22

CPU_TEST5

C 613 *.1U_10V_X7R_04

H_CPURST# 1"<L<5"

no decoupling should be

placed on the

GTLREF pin

H_ REQ # [4: 0 ]5

CPUR S VD0 6

R oute H_TH ERMD A and

H _THER MDC on s ame l ayer .

10 mil trace on 10 mil spacing.

Layout Note:

R392 1K_1% _04

H_BR0# 5

CLK_CPU_BCLK 2

1.05VS2,4,5,7,9,10,22,25,37,39

H_ T MS

H_D#52

D6 SC S751 V-4 0

Zo= 55O? 5%

D03B

R6 4

*100K_04

H_D#37

COM P3

H_ A# 2 8

H_ R EQ# 2

H_ A# 1 3

H_ A# 6

H_ A# 3

R70 *20mil_short

COMP[3:0]

traces should be at least 25 mils (> 50 mils

preferred) away from any other toggling

signal.

H_ DIN V# 05

C2 0 1

1U_6.3V_04

R2 9

27 . 4 _ 1% _ 0 4

R87

* 20K_04

H_D#51

H_D#26

C2 21

*.1U_16V_04

SMD_CPU_THERM 34

H_PR EQ#

H_ A# 2 2

CPUR S VD0 4

R92

* 100K_04

H_ A# 9

H_ A# 1 5

H_ A# 1 4

H_D#19

R60 56_04

H_ N MI22

H_D#6

H_ DIN V# 15

CPU_TEST3

R 67 *0_04

D03A-0313

H_ A# [3 5:3 ]5

H_D#56

ADDR

GROUP_0

AD D R

GROUP _1

CONTROLXDP/ITP SIGNALS

H CL K

THERMAL

RESERVED

IC H

U2 2A

Pen ry n

D22

A22

A21

AD 4

AD 3

AD 1

AC 4

C20

F21

D20

AC 2

AC 1

D21

AC 5

AA 6

AB 3

A24

B25

AB 5

AB 6

AA4

AB2

AA3

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[3]#

A[30]#

A[31]#

R SVD[0 1 ]

R SVD[0 2 ]

R SVD[0 3 ]

R SVD[0 4 ]

R SVD[0 5 ]

R SVD[0 6 ]

R SVD[0 7 ]

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A20M#

ADS #

AD STB[0]#

AD STB[1]#

R SVD[0 8 ]

BC LK[0 ]

BC LK[1 ]

BNR #

BPM [0] #

BPM [1] #

BPM [2] #

BPM [3] #

BPRI #

BR 0#

DBR #

DBSY #

DEFER#

DR DY #

FER R#

HIT#

HITM #

IERR #

IG NN E#

IN IT#

LINT0

LINT1

LOCK #

PR DY #

PREQ #

PRO CHO T #

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

R ESET#

RS[0]#

RS[1]#

RS[2]#

SM I#

STPC LK#

TCK

TDI

TD O

THER MTRIP #

TH E R M D A

THE RMD C

TMS

TR D Y #

TR S T #

A[32]#

A[33]#

A[34]#

A[35]#

R SVD[0 9 ]

R34 649_1%_06

H_D#38

H_D#61

H_A#[35:3]5

H_ T DI

H_ A# 1 7

H_D#33

H_NMI

H_INTR

H_A20M#

H_DPSLP#

H_IGNNE#

H_INIT#

H_SMI#

H_STPCLK#

0.5" < L< 12"

CPU TO ICH with same

ground plane

H_ T MS

CPUR S VD0 9

CPUR S VD0 2

R6 6

* 1 0m i l _s h or t

R57 56_04

H_D#4

H_ A# 3 0

H_ IN TR22

H_D#36

H_D#35

H_D#40

H_D#43

H_ADS# 5

H_D#47

H_HIT# 5

H_ A# 2 3

H_ A# 7

Lay out Note:

PSI#41

Layout Note:

THE RM_R ST#34

D03-0221

H_DBSY# 5

H_CPURST# 5

H_A20M#22

H_ IG NNE #22

COM P1

H_ A# 3 5

H_ R EQ# 3

H_D#45

R3 9 7

27.4_1%_04

H_ D# [6 3: 0] 5

H_D#62

H_ TH ERM DA

H_D#17

CPU_TEST6

H_ BP M1 #

H_ DST BN #15

H_D#13

H_D#41

H_ BP M2 #

H_D#28

H_ BP M0 #

Layout note:

PM _TH RM# 2 4

CPU _BSE L02

H_ BP M3 #

D03-0221

1.05VS

H_INIT# 22

H_ A# 2 9

H_ A# 1 6

R74

*10K_04

H_BPRI# 5

H_ A# 2 5

H_D#24

COMP2CPU_TEST2

COM P2

COMP1

H_D#3

TO POWER PAGE

H_DEFER# 5

COMP0

CPU_TEST4

H_D#39

CPUR S VD0 5

R 30 54.9_1%_04

VDD 3

1. 0 5 V S

H_D#32

D03-0221

H_DINV#2 5

THER M_ALERT# 34

H_D#10

Z0303

H_ SM I#22

H_D#18

If PROCHOT# is routed between CPU, IMVP and MCH,

pull-up resistor has to be 68 ohm ? 5%. If not

use, pull-up resistor has to be 56 ohm ? 5%

H_PWRGD <12" (CPU TO ICH9M)

H_ADS TB# 05

Near to Thermal

IC

H_ T RST #

H_ DST BN #05

H_D#54

3.3VS2,6, 7,10,12,13,14,15,22,23,24,25,26,27,28,29,30,31,32,33,34,35,39,41,43

H_ PRD Y #

COMP3

H_DSTBP# 05

PM _TH RM TR IP# 7,22

H_D#27

H_ A# 3 4

H_PWRGD 22

H_ T HER MDC

H_ R EQ# 1

H_ T HER MDA

<12 in che s

H_DSTBP#3 5

H_D#59

H_DSTBN#3 5

H_D#55

H_D#49

H_ R EQ# 4

H _DPSLP# 2 2

H_D#58

H_PREQ #

H_TRDY# 5

H_ A# 1 8

H_D#21

CPU _BSE L22

Z0302

H_ IERR #

R394

2K_1%_04

H_HITM# 5

CPU _BSE L12

CPU_TEST1

H_D#46

H_ PRO CH OT#

H_D#25

H_F ERR#22

H_CPUSLP# 5

H_D#14

3.3V

H_ P R OC HOT#

H_D#30

R6 9

4.7K_04

H_LOCK# 5

H_D#44

10mi ls

H_ A# 8

H_D#[63:0]5

IT P_ DBR S T#

Z0306

R6 5

10 K _ 0 4

H_D#48

C2 2 5

* .01U_16V_04

H_RS#2 5

H_D#16

CPUR S VD0 3

H_DINV#3 5

H_DPWR# 5

R3 9 5

54.9_1%_04

H_ A# 3 1

Zo= 55O? 5%

H_ D# [6 3: 0] 5

H_DPRSTP# 7,22,41

H_ T RS T #

H_D#34

H_D#15

H_D#60

H_D#1

D03-0221

H_D#8

H_D#[63:0]5

VD D322,34,35,36,40

H_ A# 1 1

H_D#23

R 33 54.9_1%_04

H_ A# 4

H_ T DI

COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms

COMP1, COMP3: 0.5" Max, Zo=55 Ohms

Best estimate is 18 mils wide trace for outer

layers and 14 mils wide trace if on internal

layers.

H_D#29

H_ T CK

H_D#9

H_AD STB#15

Within 2.0"

of th e CP U

H_D#5

H_D#57

CPUR S VD0 1

H_DSTBP# 15

H_D#31

H _B NR# 5

H_ A# 1 9

Z0307

H_ A# 1 0

Zo= 55O? 5%

CPU_TEST7

R56 *1K_04

H_ ST PCL K #22

H_ A# 1 2

H_ A# 5

H_ R EQ# 0

H_ A# 2 7

H_D#20

H_DSTBN#2 5

NEAR EC

CPUR S VD0 8

H_ A# 2 0

CPUR S VD0 7

*A O 34 0 9

DA TA GR P 0 DA TA GR P 1

DAT A GRP 2DAT A GRP 3

MISC

U22B

Penryn

R2 6

U2 6

AA1

E22

F24

J2 4

J2 3

H2 2

F26

K22

H2 3

N2 2

K25

P26

R2 3

E26

L2 3

M2 4

L2 2

M2 3

P25

P23

P22

T2 4

R2 4

L2 5

G2 2

T2 5

N2 5

Y22

AB24

V24

V26

V23

T22

U2 5

U2 3

F23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

AE24

AD 24

G2 5

AA21

AB22

AB21

AC 26

AD 20

AE22

AF2 3

AC 25

AE21

AD 21

E25

AC 22

AD 23

AF2 2

AC 23

E23

K24

G2 4

AF1

H2 5

N2 4

U2 2

AC 20

D2 4

J2 6

L2 6

Y26

AE25

H2 6

M2 6

AA26

AF2 4

AD26

AE6

C2 4

B22

B23

C2 1

D2 5

AF2 6

A26

C2 3

CO MP[0 ]

CO MP[1 ]

CO MP[2 ]

CO MP[3 ]

D[0 ]#

D[1 ]#

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[2 ]#

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

D[29]#

D[3 ]#

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

D[4 ]#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[5 ]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[6 ]#

D[60]#

D[61]#

D[62]#

D[63]#

D[7 ]#

D[8 ]#

D[9 ]#

TEST5

DIN V [0 ]#

DIN V [1 ]#

DINV[2]#

DINV[3]#

DPRSTP#

DPSLP#

DPWR#

DST BN [0]#

DST BN [1]#

DST BN[2 ]#

DST BN[3 ]#

DSTBP[0]#

DSTBP[1]#

DS TBP[2]#

DS TBP[3]#

GT L R EF

PSI#

PW RG OOD

SLP#

TEST3

BSEL[0]

BSEL[1]

BSEL[2]

TEST2

TEST4

TEST6

TEST1

TEST7

H_DRDY# 5

H_D#11

H_D#2

V_TH RM

H_RS#1 5

H_ IER R#

R 31 54.9_1%_04

H_ A# 3 3

H_ A# 3 2

H_D#63

W83L771AWG

VD D

D+

D-

TH ERM

GND

ALER T

SD ATA

SC LK

Layout note:

Zo =55 ohm, 0.5 "max for GTLR EF

ITP _D BRST #

C1 9 8

100 0 P_ 50 V_ 0 4

H_ A# 2 4

H_ TH ERM DC

H_ T CK

R28

54.9_1% _04

R68

4.7K_04

H_D#42

H_ T DO

CPU_GTLREF

H_D#53

CLK_CPU_BCLK# 2

R62 *1K_04

R 32 54.9_1%_04

DESIGN GUIDE P.65

THERMAL SENSER

H _TD I

C irc ul t: 54 .9 o hm ch eck 1 50 oh m

H_RS#0 5

H_D#0

H_ A# 2 6

H_D#12

3.3VS

3.3V14,15,22,23,24,25,26,28,30,31,35,37,38

R416 *1K_04

*2 N 7 0 02 W