Cypress Switching Waveforms continued, Advance, CY14E108L, CY14E108N, + Feedback, Data Valid

Models: CY14E108N CY14B102N

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Switching Waveforms (continued)

ADVANCE

CY14E108L, CY14E108N

Switching Waveforms (continued)

Figure 6. SRAM Read Cycle #2: CE and OE Controlled[10, 21, 23]

ADDRESS

CE

OE

BHE , BLE

DQ (DATA OUT)

ICC

tRC

tACE

tLZCE

tDOE

tLZOE

tDBE

tLZBE

tPU ADDRESS ACTIVE

STANDBY

tPD

tHZCE

tHZOE

tHZCE tHZBE

DATA VALID

 

Figure 7. SRAM Write Cycle #1: WE Controlled[13, 21, 22, 23]

 

 

tWC

 

ADDRESS

 

 

 

 

 

tSCE

tHA

 

 

 

CE

 

 

 

 

 

tAW

 

 

tSA

tPWE

 

WE

 

 

 

 

 

BHE , BLE

 

tBW

 

 

 

 

 

 

tSD

tHD

DATA IN

 

DATA VALID

 

 

 

tHZWE

tLZWE

 

 

HIGH IMPEDANCE

DATA OUT

PREVIOUS DATA

 

 

 

Notes

22.CE or WE must be >VIH during address transitions.

23.BHE and BLE are applicable for x16 configuration only.

Document Number: 001-45524 Rev. *A

Page 11 of 20

[+] Feedback

Page 11
Image 11
Cypress Switching Waveforms continued, Advance, CY14E108L, CY14E108N, SRAM Write Cycle #1 WE Controlled 13, 21, 22