ADVANCE
CY14E108L, CY14E108N
Switching Waveforms (continued)
Figure 8. SRAM Write Cycle #2: CE Controlled[13, 21, 22, 23]
ADDRESS
tSA
CEWE
BHE , BLE
DATA IN
DATA OUT
tWC
tSCE
tAW
tPWE
tBW
tSD
DATA VALID
HIGH IMPEDANCEtHA
tHD
Figure 9. AutoStore or Power Up RECALL[24]
| STORE occurs only | No STORE occurs | |
VCC | if a SRAM write | without atleast one | |
has happened | SRAM write | ||
|
VSWITCH |
|
tVCCRISE |
|
AutoStore | tSTORE |
tSTORE |
tHRECALL
Read & Write Inhibited
Note
24. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
Document Number: | Page 12 of 20 |
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