ADVANCE
CY14E108L, CY14E108N
AC Switching Characteristics
In the following table, the AC switching characteristics are listed.
| Parameters | Description | 20 ns | 25 ns | 45 ns | Unit | |||||
| Cypress |
| Alt | Min | Max | Min | Max | Min | Max | ||
| Parameters |
| Parameters |
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SRAM Read Cycle |
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tACE | tACS | Chip Enable Access Time |
| 20 |
| 25 |
| 45 | ns | ||
tRC[10] | tRC | Read Cycle Time | 20 |
| 25 |
| 45 |
| ns | ||
t | [11] | t | AA | Address Access Time |
| 20 |
| 25 |
| 45 | ns |
| AA |
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tDOE | tOE | Output Enable to Data Valid |
| 10 |
| 12 |
| 20 | ns | ||
tOHA | tOH | Output Hold After Address Change | 3 |
| 3 |
| 3 |
| ns | ||
tLZCE[12] | tLZ | Chip Enable to Output Active | 3 |
| 3 |
| 3 |
| ns | ||
tHZCE[12] | tHZ | Chip Disable to Output Inactive |
| 8 |
| 10 |
| 15 | ns | ||
tLZOE[12] | tOLZ | Output Enable to Output Active | 0 |
| 0 |
| 0 |
| ns | ||
tHZOE[12] | tOHZ | Output Disable to Output Inactive |
| 8 |
| 10 |
| 15 | ns | ||
tPU[10] | tPA | Chip Enable to Power Active | 0 |
| 0 |
| 0 |
| ns | ||
tPD[10] | tPS | Chip Disable to Power Standby |
| 20 |
| 25 |
| 45 | ns | ||
tDBE | - | Byte Enable to Data Valid |
| 10 |
| 12 |
| 20 | ns | ||
tLZBE | - | Byte Enable to Output Active | 0 |
| 0 |
| 0 |
| ns | ||
tHZBE | - | Byte Disable to Output Inactive |
| 8 |
| 10 |
| 15 | ns | ||
SRAM Write Cycle |
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tWC | tWC | Write Cycle Time | 20 |
| 25 |
| 45 |
| ns | ||
tPWE | tWP | Write Pulse Width | 15 |
| 20 |
| 30 |
| ns | ||
tSCE | tCW | Chip Enable To End of Write | 15 |
| 20 |
| 30 |
| ns | ||
tSD | tDW | Data Setup to End of Write | 8 |
| 10 |
| 15 |
| ns | ||
tHD | tDH | Data Hold After End of Write | 0 |
| 0 |
| 0 |
| ns | ||
tAW | tAW | Address Setup to End of Write | 15 |
| 20 |
| 30 |
| ns | ||
tSA | tAS | Address Setup to Start of Write | 0 |
| 0 |
| 0 |
| ns | ||
tHA | tWR | Address Hold After End of Write | 0 |
| 0 |
| 0 |
| ns | ||
tHZWE[12,13] | tWZ | Write Enable to Output Disable |
| 8 |
| 10 |
| 15 | ns | ||
tLZWE[12] | tOW | Output Active after End of Write | 3 |
| 3 |
| 3 |
| ns | ||
tBW | - | Byte Enable to End of Write | 15 |
| 20 |
| 30 |
| ns |
Notes
10.WE must be HIGH during SRAM read cycles.
11.Device is continuously selected with CE and OE both LOW.
12.Measured ±200 mV from steady state output voltage.
13.If WE is LOW when CE goes LOW, the output goes into high impedance state.
Document Number: | Page 9 of 20 |
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