Cypress CY24271 CY24272, Clk Clkb, tDC,ERR = tPW-i - tPW-i+1 and tPW-i+1 - tPW+i+1, t PW-i, V H

CY24272

Figure 4. Input and Output Waveforms

V H

80%

V (t)

20%

V L

tR

tF

Figure 5. Crossing Point Voltage

CLK

CLKB

Vx+

Vx.nom

Vx-

Figure 6. Cycle-to-cycle Jitter

CLK

CLKB

tCYCLE,i tCYCLE,i+1

tJ = tCYCLE,i - tCYCLE,i+1 over 10,000 consecutive cycles

CLK

CLKB

Figure 7. Cycle-to-cycle Duty-cycle Error

tPW-(i)
	tPW+(i)	tPW-(i+1)	tPW+(i+1)

tCYCLE,(i) tCYCLE,(i+1)

tDC,ERR = tPW-(i) - tPW-(i+1) and tPW-(i+1) - tPW+(i+1)

Document Number: 001-42414 Rev. ** Page 11 of 13

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