Cypress CY24272, CY24271 manual AC Operating Conditions, DC Electrical Specifications

										CY24272
AC Operating Conditions
The AC operating conditions follow.[6]
Parameter		Description			Condition			Min	Max	Unit
tCYCLE,IN		REFCLK, REFCLKB input cycle time		REFSEL = 0, /BYPASS = High				9	11	ns
				REFSEL = 1, /BYPASS = High				7	8	ns
				/BYPASS = Low				4	–	ns
tJIT,IN(cc)		Input Cycle to Cycle Jitter[9]						–	185	ps
tDCIN[10]		Input Duty Cycle		Over 10,000 cycles				40%	60%	tCYCLE
tRIN / tFIN		Rise and Fall Times		Measured at 20%–80% of input				175	700	ps
				voltage for REFCLK and
				REFCLKB inputs
ΔtRIN / tFIN		Rise and Fall Times Difference						–	150	ps
pMIN[11]		Modulation Index for triangular modulation						–	0.6	%
		Modulation Index for non-triangular modulation						–	0.5[12]	%
fMIN[11]		Input Frequency Modulation						30	33	kHz
tSR,IN		Input Slew Rate (measured at 20%–80% of						1	4	V/ns
		input voltage) for REFCLK
CIN,REF		Capacitance at REFCLK inputs						–	7	pF
CIN,CMOS		Capacitance at CMOS inputs						–	10	pF
fSCL		SMBus clock frequency input in SCL pin						DC	100	kHz
DC Electrical Specifications
Parameter			Description				Min	Typ	Max	Unit
VOX[6]		Differential output crossing point voltage[13]					–	1.08	–	V
VCOS[6]		Output voltage swing (peak-to-peak single-ended)[14]					–	400	–	mV
VOL,ABS		Absolute output low voltage at CLK[3:0], CLK[3:0]B[15]					0.85	–	–	V
VISET		Reference voltage for swing controlled current, IREF					0.98	1.0	1.02	V
IDD[7]		Power Supply Current at 2.625V, fref = 100 MHz, and fout = 300 MHz					–	–	85	mA
IDD[7]		Power Supply Current at 2.625V, fref = 133 MHz, and fout = 667 MHz					–	–	125	mA
I	I	Ratio of output low current to reference current[16]					6.8	7.0	7.2
OL/ REF
IOL,ABS		Minimum current at VOL,ABS[17]					25	–	–	mA
VOL,SDA		SDA output low voltage at test condition of SDA output low current = 4 mA					–	–	0.4	V
IOL,SDA		SDA output low voltage at test condition of SDA voltage = 0.8V					6	–	–	mA
IOZ		Current during High Z per pin at CLK[3:0], CLK[3:0]B					–	–	10	μA
Z	OUT	Output dynamic impedance when clock output signal is at V			OL	= 0.9V[18]	1000	–	–	Ω

Notes

9.Jitter measured at crossing points and is the absolute value of the worst case deviation.

10.Measured at crossing points.

11.If input modulation is used; input modulation is allowed but not required.

12.The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.

13.VOX is measured on external divider network.

14.VCOS = (clock output high voltage – clock output low voltage), measured on the external divider network.

15.VOL_ABS is measured at the clock output pins of the package.

16.IREF is equal to VISET/RRC.

17.Minimum IOL,ABS is measured at the clock output pin with RRC = 266 ohms or less.

18.ZOUT is defined at the output pins as (0.94V – 0.90V)/(I0.94 – I0.90) under conditions specified for IOL, ABS.

Document Number: 001-42414 Rev. ** Page 8 of 13

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