Package Diagram | Cypress CY7B9911V specs

CY7B9911V 3.3V RoboClock+™

Package Diagram

Figure 10. 32-Pin Plastic Leaded Chip Carrier J65

51-85002-*B

Document Number: 38-07408 Rev. *D

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Cypress CY7B9911V manual Package Diagram, Pin Plastic Leaded Chip Carrier J65

Contents

Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion Court Signal Name Description Pin ConfigurationPin Definitions Block Diagram Description Typical Outputs with FB Connected to a Zero Skew Output Test Mode Zero Skew and Zero Delay Clock Driver Operational Mode Descriptions Inverted Output Connections Multi-Function Clock Driver Maximum Ratings Electrical CharacteristicsOperating Range Range Capacitance Switching Characteristics 5 OptionAC Test Loads and Waveforms Parameter Description CY7B9911V-7 Unit Min Typ Max Switching Characteristics 7 Option AC Timing Diagrams Accuracy ps Ordering Code Package Type Operating Range Ordering InformationPb-Free CY7B9911V-5JXCT Pin Plastic Leaded Chip Carrier J65 Package Diagram Document History Issue Date Orig. Description of Change