CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Figure 16. Interrupt Timing Diagram
Left Side Sets INTR : | tWC |
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ADDRESSL | WRITE 1FFF (OR 1/3FFF) |
CE L | tHA[49] |
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R/WL |
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INTR |
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| tINS [50] |
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Right Side Clears INTR : |
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| RC |
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ADDRESSR |
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| READ 7FFF |
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CER |
tINR[50] |
R/WR |
OE R |
INTR |
Right Side Sets INTL:
ADDRESSR
CE R
R/WR
INTL
tWC |
WRITE 1FFE (OR 1/3FFE) |
tHA[49] |
tINS[50] |
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Left Side Clears INT L: |
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| tRC |
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ADDRESSR | READ 7FFE |
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| OR 1/3FFE) |
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CE L |
tINR[50] |
R/W L |
OE L |
INT L |
Notes
49.tHA depends on which enable pin (CEL or R/WL) is deasserted first.
50.tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: | Page 16 of 19 |
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