CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 9 of 19
Figure 4. AC Test Loads and Waveforms
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALLINPUT PULSES
(a)N ormal Load (Load 1)
R1= 590Ω
3.3V
OUTPUT
R2= 435Ω
C=30pF
V
TH
=1.4V
OUTPUT
C=30pF
(b) Thévenin Equivalent (Load 1) (c)Three-State Delay (Load 2)
R1= 590Ω
R2= 435Ω
3.3V
OUTPUT
C=5pF
R
TH
= 250Ω
≤≤
including scope and jig)
(Used for t
LZ
, t
HZ
, t
HZWE
, and t
LZWE
Switching Characteristics
Over the Operating Range
[20]
Parameter Description
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV Unit
-20 -25
Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 20 25 ns
t
AA
Address to Data Valid 20 25 ns
t
OHA
Output Hold From Address Change 3 3 ns
t
ACE[21]
CE LOW to Data Valid 20 25 ns
t
DOE
OE LOW to Data Valid 12 13 ns
t
LZOE[22, 23, 24]
OE Low to Low Z 3 3 ns
t
HZOE[22, 23, 24]
OE HIGH to High Z 12 15 ns
t
LZCE[22, 23, 24]
CE LOW to Low Z 3 3 ns
t
HZCE[22, 23, 24]
CE HIGH to High Z 12 15 ns
t
PU[24]
CE LOW to Power Up 0 0 ns
t
PD[24]
CE HIGH to Power Down 20 25 ns
t
ABE[21]
Byte Enable Access Time 20 25 ns
Write Cycle
t
WC
Write Cycle Time 20 25 ns
t
SCE[21]
CE LOW to Write End 15 20 ns
t
AW
Address Valid to Write End 15 20 ns
t
HA
Address Hold From Write End 0 0 ns
t
SA[21]
Address Setup to Write Start 0 0 ns
Notes
20.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OI
/I
OH
and 30 pF load capacitance.
21.To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
SCE
time.
22.At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
23.Test conditions used are Load 3.
24.This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure12.
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