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| CY7C024AV/024BV/025AV/026AV | ||
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| CY7C0241AV/0251AV/036AV | ||
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Pin Definitions |
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| Left Port |
| Right Port | Description |
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| L |
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| R | Chip Enable |
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| CE | CE | ||||||||||||||||||||||||
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| L |
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| R | Read and Write Enable |
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| R/W | R/W | ||||||||||||||||||||||||
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| L |
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| R | Output Enable |
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| OE | OE | ||||||||||||||||||||||||
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| Address |
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| Data Bus Input and Output |
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| L |
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| R | Semaphore Enable |
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| SEM | SEM | ||||||||||||||||||||||||
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| L |
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| R | Upper Byte Select |
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| UB | UB | ||||||||||||||||||||||||
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| L |
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| R | Lower Byte Select |
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| LB | LB | ||||||||||||||||||||||||
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| L |
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| R | Interrupt Flag |
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| INT | INT | ||||||||||||||||||||||||
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| L |
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| R | Busy Flag |
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| BUSY | BUSY | ||||||||||||||||||||||||
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| Master or Slave Select |
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| M/S |
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| VCC |
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| Power |
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| GND |
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| Ground |
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| NC |
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| No Connect |
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Architecture
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of
Functional Description
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and 16K ×16/18 dual port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. There are two ports permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16
Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic has eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a Chip Select (CE) pin.
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV0251AV/036AV are available in
Write Operation
Data must be set up for a duration of tSD before the rising edge of RW to guarantee a valid write. A write operation is controlled by either the RW pin (see Figure 8 on page 12) or the CE pin (see Figure 9 on page 12). Required inputs for
If a location is being written to by one port and the opposite port tries to read that location, there must be a port to port flowthrough delay before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wants to access a semaphore flag, then the SEM pin and OE must be asserted.
Interrupts
The upper two memory locations are for message passing. The
highest memory location (FFF for the CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
Document #: | Page 5 of 19 |
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