Cypress CY7C1146V18, CY7C1148V18, CY7C1150V18, CY7C1157V18 Logic Block Diagram (CY7C1146V18), Logic Block Diagram (CY7C1157V18)

CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Document Number: 001-06621 Rev. *D Page 2 of 27
Logic Block Diagram (CY7C1146V18)
Logic Block Diagram (CY7C1157V18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W DQ[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS[1:0]
VREF
Write Add. Decode
88
LD
Control
20
1M x 8 Array
1M x 8 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
8
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W DQ[8:0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS[0]
VREF
Write Add. Decode
99
LD
Control
20
1M x 9 Array
1M x 9 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
9
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