300 | Cypress CY7C1146V18, CY7C1148V18, CY7C1150V18, CY7C1157V18

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1146V18-300BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1157V18-300BZC

	CY7C1148V18-300BZC

	CY7C1150V18-300BZC

	CY7C1146V18-300BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1157V18-300BZXC

	CY7C1148V18-300BZXC

	CY7C1150V18-300BZXC

	CY7C1146V18-300BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1157V18-300BZI

	CY7C1148V18-300BZI

	CY7C1150V18-300BZI

	CY7C1146V18-300BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1157V18-300BZXI

	CY7C1148V18-300BZXI

	CY7C1150V18-300BZXI

Document Number: 001-06621 Rev. *D

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Cypress CY7C1146V18, CY7C1148V18, CY7C1150V18, CY7C1157V18 manual 300

Contents

Configurations FeaturesSelection Guide Functional Description Description 375 MHz 333 MHz 300 MHz Unit Logic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18 CY7C1146V18 2M x Pin ConfigurationsCY7C1157V18 2M x TMS CY7C1150V18 512K x CY7C1148V18 1M xBWS TMS TDI Pin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Negative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for Jtag Functional Overview SRAM#1 SRAM#2 Truth TableMaster Operation Write Cycle Descriptions When the Data portion of a write sequence is activeComments Remains unaltered Written into the device Write cycle descriptions of CY7C1148V18 follows, 3Written into the device. D359 remains unaltered Into the device. D80 and D3518 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max Unit TAP Timing and Test Condition TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan Order Power Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL Constraints Maximum Ratings Electrical CharacteristicsOperating Range AC Input Requirements Thermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Cypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL Timing Read/Write/Deselect Sequence Switching WaveformsNOP Read NOP Write Ordering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package Diagram Document History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP