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Cypress CY7C1157V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Models: CY7C1146V18 CY7C1157V18 CY7C1150V18 CY7C1148V18

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						CY7C1146V18, CY7C1157V18
						CY7C1148V18, CY7C1150V18

Pin Definitions (continued)

	Pin Name		IO			Pin Description
			Input	DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
	DOFF
				timings in the DLL turned off operation are different from those listed in this data sheet. For normal
				operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves
				in DDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to
				167 MHz with DDR-I timing.

	TDO		Output	TDO for JTAG.

	TCK		Input	TCK Pin for JTAG.

	TDI		Input	TDI Pin for JTAG.

	TMS		Input	TMS Pin for JTAG.

	NC		N/A	Not Connected to the Die. Tie to any voltage level.

	NC/36M		N/A	Not Connected to the Die. Tie to any voltage level.

	NC/72M		N/A	Not Connected to the Die. Tie to any voltage level.

	NC/144M		N/A	Not Connected to the Die. Tie to any voltage level.

	NC/288M		N/A	Not Connected to the Die. Tie to any voltage level.

	VREF		Input-	Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and
			Reference	AC measurement points.

	VDD		Power Supply	Power Supply Inputs to the Core of the Device.
	VSS		Ground	Ground for the Device.
	VDDQ		Power Supply	Power Supply Inputs for the Outputs of the Device.

Document Number: 001-06621 Rev. *D

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Cypress CY7C1157V18, CY7C1148V18 TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag, Ground for the Device

Contents

Description 375 MHz 333 MHz 300 MHz Unit FeaturesConfigurations Selection Guide Functional Description Logic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18 TMS Pin ConfigurationsCY7C1146V18 2M x CY7C1157V18 2M x TMS TDI CY7C1148V18 1M xCY7C1150V18 512K x BWS Negative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. When TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for Jtag Functional Overview Operation Truth TableSRAM#1 SRAM#2 Master Remains unaltered When the Data portion of a write sequence is activeWrite Cycle Descriptions Comments Into the device. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Written into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State Diagram Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP Controller TAP Timing and Test Condition TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan Order DLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up Waveforms AC Input Requirements Electrical CharacteristicsMaximum Ratings Operating Range Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and Waveforms DLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min Max Read NOP Write Switching WaveformsRead/Write/Deselect Sequence NOP Ordering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package Diagram VKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR