Contents
Main
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Configurations
Functional Description
Selection Guide
Logic Block Diagram (CY7C1146V18)
Logic Block Diagram (CY7C1157V18)
1M x 8 Array 1M x 8 Array
1M x 9 Array 1M x 9 Array
Logic Block Diagram (CY7C1148V18)
Logic Block Diagram (CY7C1150V18)
512K x 18 Array 512K x 18 Array
256K x 36 Array 256K x 36 Array
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
Pin Configurations
CY7C1146V18 (2M x 8)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1157V18 (2M x 9)
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
Pin Configurations
CY7C1148V18 (1M x 18)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1150V18 (512K x 36)
CY7C1146V18, CY7C1157V18
Pin Definitions
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
Pin Definitions
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
Functional Overview
Read Operations
Write Operations
Byte Write Operations
Truth Table
BUS MASTER (CPU or ASIC)
SRAM#1
SRAM#2
Write Cycle Descriptions
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access PortTest Clock
Test Mode Select
Test Data-In (TDI)
Page
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
TAP Controller State Diagram
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
TAP Controller Block Diagram
TAP Electrical Characteristics
TAP AC Switching Characteristics
TAP Timing and Test Condition
Identification Register Definitions
Scan Register Sizes
Instruction Codes
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
Boundary Scan Order
Power Up Sequence in DDR-II+ SRAM
Power Up Sequence
DLL Constraints
Power Up Waveforms
K K
Maximum Ratings
Operating Range
Electrical Characteristics
AC Input Requirements
Capacitance
Thermal Resistance
AC Test Loads and Waveforms
Switching Characteristics
Switching Waveforms
Read/Write/Deselect Sequence
READ NOP WRITE
READ READ
12345678910
Page
Ordering Information
Package Diagram
Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
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SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
1.40 MAX.
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