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Cypress CY7C1157V18 manual Switching Waveforms, Read/Write/Deselect Sequence, Nop, Read NOP Write

Models: CY7C1146V18 CY7C1157V18 CY7C1150V18 CY7C1148V18

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Switching Waveforms

Read/Write/Deselect Sequence

Figure 7. Waveform for 2.0 Cycle Read Latency[29, 30, 31]

NOP

tKH

	READ	READ	NOP	NOP	NOP	WRITE	WRITE	READ	NOP	NOP
	2	3	4	5	6	7	8	9	10	11	12
tKL	tCYC	tKHKH

LD tSC tHC

R/W

A	A0	A1		A2	A3	A4
A
	tSA tHA	tQVLD				tQVLD
QVLD					tHD	tHD
					tHD	tHD
					tSD
DQ		Q00	Q01 Q10	Q11	D21	D30 D31	Q40 Q41
DQ
		tCLZ	tDOH	tCHZ
		tCO		tCQD
	(Read Latency = 2.0 Cycles)
		tCCQO		tCQDOH
		tCQOH
CQ			t CCQO		tCQH	tCQHCQH
		tCQOH	t CCQO		tCQH	tCQHCQH
		tCQOH
CQ
						DON’T CARE	UNDEFINED

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.

30.Outputs are disabled (High-Z) one clock cycle after a NOP.

31.The third NOP cycle between Read to Write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency operation, it may be required to avoid bus contention.

Document Number: 001-06621 Rev. *D

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Cypress CY7C1157V18, CY7C1148V18, CY7C1146V18 manual Switching Waveforms, Read/Write/Deselect Sequence, Nop, Read NOP Write

Contents

Description 375 MHz 333 MHz 300 MHz Unit FeaturesConfigurations Selection Guide Functional Description Logic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18 TMS Pin ConfigurationsCY7C1146V18 2M x CY7C1157V18 2M x TMS TDI CY7C1148V18 1M xCY7C1150V18 512K x BWS Negative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. When TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for Jtag Functional Overview Operation Truth TableSRAM#1 SRAM#2 Master Remains unaltered When the Data portion of a write sequence is activeWrite Cycle Descriptions Comments Into the device. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Written into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State Diagram Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP Controller TAP Timing and Test Condition TAP AC Switching Characteristics Instruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan Order DLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up Waveforms AC Input Requirements Electrical CharacteristicsMaximum Ratings Operating Range Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and Waveforms DLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min Max Read NOP Write Switching WaveformsRead/Write/Deselect Sequence NOP Ordering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package Diagram VKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR

Switching Waveforms

Read/Write/Deselect Sequence

Figure 7. Waveform for 2.0 Cycle Read Latency[29, 30, 31]

NOP

READ

NOP

WRITE

DON’T CARE

UNDEFINED