CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18
Power Up Sequence in DDR-II+ SRAM
During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.
Power Up Sequence
■Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW)
❐Apply VDD before VDDQ
❐Apply VDDQ before VREF or at the same time as VREF
DLL Constraints
■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.
■The DLL functions at frequencies down to 120 MHz.
■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency.
■Provide stable power and clock (K, K) for 2048 cycles to lock the DLL.
Power Up Waveforms
Figure 5. Power Up Waveforms
K
K
VDD/VDDQ
DOFF
~ ~
| ~ ~ |
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Unstable Clock | > 2048 Stable Clock | Start Normal |
Clock Start (Clock Starts after VDD/VDDQ is Stable) | Operation | |
| ||
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
Fix HIGH (tie to VDDQ)
Document Number: | Page 19 of 27 |
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