Cypress CY7C1292DV18, CY7C1294DV18 VV, /

CY7C1292DV18

CY7C1294DV18

Document #: 001-00350 Rev. *A Page 16 of 23

Power-Up Sequence in QDR-II SRAM[16]

QDR-II SRAMs must be powered up and initialized in a

predefined manner to prevent undefined operations.

Power-Up Sequence

• Apply power with DOFF tied HIGH (All other inputs can be

HIGH or LOW)

—Apply V

DD before VDDQ

—Apply V

DDQ before VREF or at the same time as VREF

• Provide stable power and clock (K, K) for 1024 cycles to

lock the DLL.

DLL Constraints

• DLL uses K clock as its synchronizing input. The input

should have low phase jitter, which is specified as tKC Var.

• The DLL will function at frequencies down to 80 MHz.

• If the input clock is unstable and the DLL is enabled, then

the DLL may lock onto an incorrect frequency, causing

unstable SRAM behavior. To avoid this, provide 1024 cycles

stable clock to relock to the desired clock frequency.

Notes:

15.It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1Kohm.

16.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.

> 1024 Stable clock

Start Normal

Operation

DOFF

Stable(< +/- 0.1V DC per 50ns )

Fix High (or tied to VDDQ)

DDQ

/DDQ

Clock Start (Clock Starts after Stable)

DDQ

Unstable Clock

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