CY7C1292DV18
CY7C1294DV18
Document #: 001-00350 Rev. *A Page 19 of 23
Switching Characteristics Over the Operating Range[22, 23]
Cypress
Parameter Consortium
Parameter Description
250 MHz 200 MHz 167 MHz
UnitMin. Ma x. Min. Max. Min. Max.
tPOWER tKHKH VDD(Typical) to the first Access[24] 111ms
tCYC tKHKL K Clock and C Clock Cycle Time 4.0 6.3 5.0 7.9 6.0 7.9 ns
tKH tKLKH Input Clock (K/K and C/C) HIGH 1.6 – 2.0 – 2.4 – ns
tKL tKHKHInput Clock (K/K and C/C) LOW 1.6 – 2.0 – 2.4 – ns
tKHKHtKHCH
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge) 1.8 – 2.2 – 2.7 – ns
tKHCH tKHKH
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge) 0.0 1.8 0.0 2 .2 0.0 2.7 ns
Set-up Times
tSA tAVKH Address Set-up to Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
tSC tIVKH Control Set-up to K Clock Rise (RPS, WPS)0.35 – 0.4 – 0.5 – ns
tSCDDR tIVKH
Double Data Rate Control Set-up to Clock
(K/K) Rise (BWS0, BWS1, BWS3, BWS4) 0.35 – 0.4 – 0.5 – ns
tSD tDVKH D[X:0] Set-up to Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
Hold Times
tHA tKHAX Address Hold after Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
tHC tKHIX Control Hold after K Clock Rise (RPS, WPS)0.35 – 0.4 – 0.5 – ns
tHCDDR tKHIX
Double Data Rate Control Hold after Clock
(K/K) Rise (BWS0, BWS1, BWS3, BWS4) 0.35 – 0.4 – 0.5 – ns
tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
Output Times
tCO tCHQV
C/C Clock Rise (or K/K in Single Clock Mode)
to Data Valid – 0.45 – 0.45 – 0.50 ns
tDOH tCHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active) –0.45 – -0.45 – -0.50 – ns
tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.50 ns
tCQOH tCHCQX Echo Clock Hold after C/C Clock Rise –0.45 – –0.45 – –0.50 – ns
tCQD tCQHQV Echo Clock High to Data Valid – 0.30 – 0.35 – 0.40 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.30 – –0.35 – –0.40 – ns
tCHZ tCHQZ
Clock (C/C) Rise to High-Z
(Active to High-Z)[25,26] – 0.45 – 0.45 – 0.50 ns
tCLZ tCHQX1 Clock (C/C) Rise to Low-Z[25,26] –0.45 – –0.45 – –0.50 – ns
DLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock DLL Lock Time (K, C) 1024 – 102 4 – 1024 – cycles
tKC Reset tKC Reset K Static to DLL Reset 30 – 30 – 30 – ns
Notes:
23.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
24.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
25.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
26.At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
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