Cypress CY7C1292DV18, CY7C1294DV18 manual Functional Overview

			CY7C1292DV18
			CY7C1294DV18
Pin Definitions (continued)
	Pin Name	I/O	Pin Description
		Input	DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device.
	DOFF
			The timings in the DLL turned off operation will be different from those listed in this data sheet.
	TDO	Output	TDO for JTAG.
	TCK	Input	TCK pin for JTAG.
	TDI	Input	TDI pin for JTAG.
	TMS	Input	TMS pin for JTAG.
	NC	N/A	Not connected to the die. Can be tied to any voltage level.
	NC/18M	N/A	Not connected to the die. Can be tied to any voltage level.
NC/36M		N/A	Not connected to the die. Can be tied to any voltage level.
NC/72M		N/A	Not connected to the die. Can be tied to any voltage level.
NC/144M		N/A	Not connected to the die. Can be tied to any voltage level.
NC/288M		N/A	Not connected to the die. Can be tied to any voltage level.
VREF		Input-	Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
		Reference	Outputs as well as AC measurement points.
	VDD	Power Supply	Power supply inputs to the core of the device.
	VSS	Ground	Ground for the device.
	VDDQ	Power Supply	Power supply inputs for the outputs of the device.

Functional Overview

The CY7C1292DV18 and CY7C1294DV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely elimi- nates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 18-bit data transfers in the case of CY7C1292DV18 and two 36-bit data transfers in the case of CY7C1294DV18 in one clock cycle.

Accesses for both ports are initiated on the rising edge of the positive Input Clock (K). All synchronous input timings are referenced from the rising edge of the input clocks (K and K) and all output timings are referenced to the rising edge of output clocks (C and C or K and K when in single clock mode).

All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K).

CY7C1292DV18 is described in the following sections. The same basic descriptions apply to CY7C1294DV18.

Read Operations

The CY7C1292DV18 is organized internally as 2 arrays of 256K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address is latched on the rising edge of the K Clock. The address presented to Address inputs is stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C and C or K and K when in single clock mode).

Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Output Clocks (C/C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the same K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the address is latched and the infor- mation presented to D[17:0] is stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port will ignore all inputs after the pending Write operations have been completed.

Document #: 001-00350 Rev. *A Page 5 of 23

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