Cypress CY7C1332AV25 manual Switching Characteristics 18, 19, 20, Preliminary, CY7C1330AV25

CY7C1330AV25

PRELIMINARY

CY7C1332AV25

Switching Characteristics[18, 19, 20, 21]

250

200

Parameter

Description

Unit

Min.

Max.

Min.

Max.

t

V

CC

(typical) to the First Access Read or Write[22]

1

1

ms

Power

Clock

tCYC

Clock Cycle Time

4.0

5.0

ns

FMAX

Maximum Operating Frequency

250

200

MHz

tCH

Clock HIGH

1.5

1.5

ns

tCL

Clock LOW

1.5

1.5

ns

Output Times

tCO

Data Output Valid After CLK Rise

2.0

2.25

ns

tEOV

LOW to Output Valid[17, 19, 21]

2.0

2.25

ns

OE

tDOH

Data Output Hold After CLK Rise

0.5

0.5

ns

tCHZ

Clock to High-Z[17, 18, 19, 20, 21]

2.0

2.25

ns

t

Clock to Low-Z[17, 18, 19, 20, 21]

0.5

0.5

ns

CLZ

t

HIGH to Output High-Z[18, 19, 21]

2.0

2.25

ns

OE

EOHZ

tEOLZ

LOW to Output Low-Z[18, 19, 21]

0.5

0.5

ns

OE

Set-Up Times

tAS

Address Set-Up Before CLK Rise

0.3

0.3

ns

tDS

Data Input Set-Up Before CLK Rise

0.3

0.3

ns

tWES

x Set-Up Before CLK Rise

0.3

0.3

ns

WE,

BWS

tCES

Chip Select Set-Up

0.3

0.3

ns

Hold Times

tAH

Address Hold After CLK Rise

0.6

0.6

ns

tDH

Data Input Hold After CLK Rise

0.6

0.6

ns

tWEH

x Hold After CLK Rise

0.6

0.6

ns

WE,

BW

tCEH

Chip Select Hold After CLK Rise

0.6

0.6

ns

Notes:

19.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

20.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

21.This parameter is sampled and not 100% tested.

22.This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read or write operation can be initiated.

Document No: 001-07844 Rev. *A Page 15 of 19

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