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| CY7C1330AV25 |
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| PRELIMINARY |
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Scan Register Sizes |
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Register Name |
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Instruction |
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| 3 |
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| 3 |
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Bypass |
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| 1 |
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| 1 |
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ID |
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| 32 |
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| 32 |
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Boundary Scan |
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| 70 |
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Instruction Codes |
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Instruction |
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| Description |
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EXTEST |
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| 000 |
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| Captures the Input/Output ring contents. |
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IDCODE |
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| Loads the ID register with the vendor ID code and places the register between TDI |
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| and TDO. This operation does not affect SRAM operation. |
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SAMPLE Z |
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| Captures the Input/Output contents. Places the boundary scan register between |
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| TDI and TDO. Forces all SRAM output drivers to a |
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RESERVED |
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| Do Not Use: This instruction is reserved for future use. |
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SAMPLE/PRELOAD |
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| 100 |
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| Captures the Input/Output ring contents. Places the boundary scan register |
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| between TDI and TDO. Does not affect the SRAM operation. |
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RESERVED |
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| 101 |
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| Do Not Use: This instruction is reserved for future use. |
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RESERVED |
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| Do Not Use: This instruction is reserved for future use. |
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BYPASS |
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| Places the bypass register between TDI and TDO. This operation does not affect |
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| SRAM operation. |
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Boundary Scan Order (1 Mbit x 18) |
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Bit # |
| Bump ID |
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| Bit # |
| Bump ID |
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| Bump ID |
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1 |
| 5R |
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| 18 |
| 7E |
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| 1H |
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2 |
| 6T |
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| 19 |
| 6D |
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| 3G |
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3 |
| 4P |
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| 20 |
| 6A |
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| 4D |
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4 |
| 6R |
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| 21 |
| 6C |
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| 4E |
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5 |
| 5T |
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| 22 |
| 5C |
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| 4G |
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6 |
| 7T |
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| 23 |
| 5A |
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| 4H |
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7 |
| 7P |
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| 6B |
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| 4M |
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8 |
| 6N |
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| 5B |
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| 2K |
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9 |
| 6L |
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| 26 |
| 3B |
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| 1L |
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10 |
| 7K |
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| 2B |
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| 2M |
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11 |
| 5L |
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| 3A |
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| 1N |
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12 |
| 4L |
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| 29 |
| 3C |
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| 2P |
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13 |
| 4K |
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| 30 |
| 2C |
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| 3T |
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14 |
| 4F |
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| 31 |
| 2A |
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| 2R |
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15 |
| 6H |
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| 1D |
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| 4N |
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16 |
| 7G |
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| 2E |
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| 2T |
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17 |
| 6F |
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| 2G |
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| 3R |
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Document No: | Page 11 of 19 |
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