CY7C1330AV25
PRELIMINARYCY7C1332AV25
Switching Waveforms
READ/WRITE/DESELECT Sequence (OE Controlled)[23, 24, 25, 26]
READ | DESELECT | WRITE | |||
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K
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| tAS |
| tAH |
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| tCH | ||||
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ADDRESS |
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| RA1 |
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| WA2 | ||||||||||
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READ | READ | WRITE | READ | DESELECT | WRITE | WRITE | DESELECT | ||||
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tCL |
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| RA3 |
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| WA5 |
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| WA7 | WA8 | |||||
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WE
tWES tWEH
BWSx
tWES tWEH
OE/ | tEOHZ |
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| tEOLZ |
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| t | DS | t | DH | tEOV | tDOH |
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tCLZ | tDOH |
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| tEOHZ |
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Data | Q1 |
| D2 |
| Q3 | D5 | Q6 | D7 | D8 | |
In/Out | Out |
| In |
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| Out | In | Out | In | In |
Device | tCHZ |
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| tDH |
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originally | tCO |
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deselected |
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| tDS |
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= DON’T CARE 
= UNDEFINED
Notes:
23.The combination of WE and BWSx (x = a, b, c, d for x36 and x = a, b for x18) define a write cycle (see Write Cycle Description table).
24.All chip enables need to be active in order to select the device. Any chip enable can deselect the device.
25.RAx stands for Read Address X, WAx Write Address X, Dx stands for
26.CE held LOW.
Document No: | Page 16 of 19 |
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