Contents
CY7C1330AV25
Features
Configuration
Logic Block Diagram
119-Ball BGA 14 x 22 x 2.4 mm
Pin Configurations
CY7C1332AV25
Selection Guide
CY7C1332AV25
PRELIMINARY
Pin Definitions
CY7C1330AV25
Late Write Accesses
Introduction
Sleep Mode
Pipelined Read Accesses
Write Cycle Descriptions1
ZZ Mode Electrical Characteristics
Cycle Description Truth Table1, 2, 3, 4
Write Cycle Descriptions 1
Instruction Register
IEEE 1149.1 Serial Boundary Scan JTAG
CY7C1330AV25
PRELIMINARYCY7C1332AV25
IDCODE
CY7C1330AV25
PRELIMINARYCY7C1332AV25
EXTEST
SELECT
TAP Controller State Diagram6
UPDATE-DR
UPDATE-IR
CY7C1330AV25
TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range7, 8
TAP AC Switching Characteristics Over the Operating Range 10
Identification Register Definitions
CY7C1330AV25
CY7C1332AV25
TAP Timing and Test Conditions11
PRELIMINARY
Scan Register Sizes
Instruction Codes
Boundary Scan Order 1 Mbit x
CY7C1332AV25
Boundary Scan Order 512K x
PRELIMINARY
CY7C1330AV25
CY7C1330AV25
Electrical Characteristics Over the Operating Range
Maximum Ratings
Operating Range
PRELIMINARY
Capacitance17
Thermal Resistance17
AC Test Loads and Waveforms
CY7C1332AV25
Switching Characteristics 18, 19, 20
PRELIMINARY
CY7C1330AV25
ADDRESS
Switching Waveforms
CY7C1330AV25
PRELIMINARYCY7C1332AV25
ADDRESS RA1
Switching Waveforms continued
CY7C1330AV25
PRELIMINARYCY7C1332AV25
PRELIMINARYCY7C1332AV25
Package Diagram
Ordering Information
CY7C1330AV25
Page 19 of
Document History Page
CY7C1330AV25
PRELIMINARYCY7C1332AV25