CY7C1364C

Switching Waveforms (continued)

Write Cycle Timing[18,19]

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

GW

CE

ADV

OE

Data In (D)

Data Out (Q)

 

 

tCYC

 

 

 

 

tCH

tCL

 

 

 

tADS

tADH

 

 

 

 

 

 

tADS

tADH

ADSC extends burst

 

 

 

tADS

tADH

 

 

 

 

tAS

tAH

 

 

 

 

 

A1

 

 

A2

A3

 

Byte write signals are

 

 

 

ignored for first cycle when

 

tWES tWEH

 

ADSP initiates burst

 

tWES tWEH

tCES

tCEH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADVS tADVH

 

 

 

 

 

ADV suspends burst

 

 

 

 

 

tDS tDH

 

 

 

 

 

 

 

 

High-Z

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

 

t

 

 

 

 

 

 

 

 

 

OEHZ

 

 

 

 

 

 

 

 

BURST READ

Single WRITE

 

BURST WRITE

 

 

 

Extended BURST WRITE

 

 

 

DON’T CARE

UNDEFINED

 

 

 

 

 

Note:

19. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Document #: 38-05689 Rev. *E

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Cypress CY7C1364C manual Write Cycle Timing18,19, Adv