CY7C1364C
9-Mbit (256K x 32) Pipelined Sync SRAM
Features
•Registered inputs and outputs for pipelined operation
•256K × 32 common I/O architecture
•3.3V core power supply (VDD)
•2.5V/3.3V I/O power supply (VDDQ)
•Fast
— 2.8 ns (for
•Provide
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Pentium® interleaved or linear burst sequences
•Separate processor and controller address strobes
•Synchronous
•Asynchronous output enable
•Available in
•TQFP Available with
•“ZZ” Sleep Mode Option
Functional Description[1]
The CY7C1364C SRAM integrates 256K x 32 SRAM cells with advanced synchronous peripheral circuitry and a
Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).
Address, data inputs, and write controls are registered
The CY7C1364C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are
Logic Block |
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A0, A1, A | ADDRESS |
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| REGISTER |
| 2 | A[1:0] |
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MODE |
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ADV |
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| Q1 |
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CLK |
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| BURST |
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| COUNTER |
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| CLR | AND | Q0 |
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ADSC |
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ADSP |
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| DQD |
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| DQD |
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BWD | BYTE |
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| BYTE |
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| WRITE REGISTER |
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| WRITE DRIVER |
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| DQC |
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| DQC |
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BWC | BYTE |
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| BYTE |
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| OUTPUT |
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| WRITE REGISTER |
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| WRITE DRIVER | MEMORY | SENSE | OUTPUT | DQ s | |
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| BUFFERS | ||||||
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| ARRAY | REGISTERS | |||
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| DQB | AMPS | E |
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| DQB |
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BWB | BYTE |
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| BYTE |
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| WRITE DRIVER |
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| WRITE REGISTER |
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| DQA |
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| BYTE |
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BWA | BYTE |
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| WRITE DRIVER |
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BWE | WRITE REGISTER |
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GW |
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| INPUT |
ENABLE | PIPELINED |
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CE1 | REGISTER |
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ENABLE |
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CE2 |
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CE3 |
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OE |
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ZZ | SLEEP |
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CONTROL |
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Notes:
1.For
2.CE3 is not available on 2 Chip Enable TQFP package.
Cypress Semiconductor Corporation | • | 198 Champion Court • San Jose, CA | • | |
Document #: |
| Revised September 14, 2006 |
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