Cypress CY7C1364C manual Maximum Ratings, Operating Range

CY7C1364C

Maximum Ratings

DC Input Voltage

–0.5V to VDD + 0.5V

(Above which the useful life may be impaired. For user guide-

Current into Outputs (LOW)

20 mA

Static Discharge Voltage

>2001V

lines, not tested.)

Storage Temperature

–65°C to +150°C

(per MIL-STD-883, Method 3015)

Latch-up Current

>200 mA

Ambient Temperature with

Power Applied

–55°C to +125°C

Operating Range

Supply Voltage on VDD Relative to GND

–0.5V to +4.6V

Ambient

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

Range

Temperature

VDD

VDDQ

DC Voltage Applied to Outputs

Commercial

0°C to +70°C

3.3V –

2.5V – 5% to

in tri-state

–0.5V to V

+ 0.5V

5%/+10%

VDD

Industrial

–40°C to +85°C

DDQ

Electrical Characteristics Over the Operating Range [9, 10]

Parameter

Description

Test Conditions

Min.

Max.

Unit

VDD

Power Supply Voltage

3.135

3.6

V

VDDQ

I/O Supply Voltage

for 3.3 V I/O

3.135

VDD

V

for 2.5V I/O

2.375

2.625

V

VOH

Output HIGH Voltage

for 3.3 V I/O, IOH = –4.0 mA

2.4

V

for 2.5V I/O, IOH = –1.0 mA

2.0

V

VOL

Output LOW Voltage

for 3.3 V I/O, IOL = 8.0 mA

0.4

V

for 2.5V I/O, IOL = 1.0 mA

0.4

V

VIH

Input HIGH Voltage[9]

for 3.3 V I/O

2.0

VDD + 0.3V

V

for 2.5V I/O

1.7

VDD + 0.3V

V

VIL

Input LOW Voltage[9]

for 3.3 V I/O

–0.3

0.8

V

for 2.5V I/O

–0.3

0.7

V

IX

Input Leakage Current

GND ≤ VI ≤ VDDQ

–5

5

∝A

except ZZ and MODE

Input Current of MODE

Input = VSS

–30

∝A

Input = VDD

5

∝A

Input Current of ZZ

Input = VSS

–5

∝A

Input = VDD

30

∝A

IOZ

Output Leakage Current

GND ≤ VI ≤ VDDQ, Output Disabled

–5

5

∝A

IDD

VDD Operating Supply

VDD = Max., IOUT = 0 mA,

4-ns cycle, 250 MHz

250

mA

Current

f = fMAX = 1/tCYC

5-ns cycle, 200 MHz

220

mA

6-ns cycle, 166 MHz

180

mA

ISB1

Automatic CE

VDD = Max., Device Deselected,

4-ns cycle, 250 MHz

130

mA

Power-down

VIN ≥ VIH or VIN ≤ VIL,

5-ns cycle, 200 MHz

120

Current—TTL Inputs

f = fMAX = 1/tCYC

6-ns cycle, 166 MHz

110

ISB2

Automatic CE

VDD

= Max., Device Deselected,

All speeds

40

mA

Power-down

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

Current—CMOS Inputs

f = 0

ISB3

Automatic CE

VDD = Max., Device Deselected,

4-ns cycle, 250 MHz

120

mA

Power-down

or VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

5-ns cycle, 200 MHz

110

Current—CMOS Inputs

f = fMAX = 1/tCYC

6-ns cycle, 166 MHz

100

ISB4

Automatic CE

VDD

= Max., Device Deselected,

All speeds

40

mA

Power-down

VIN ≥ VIH or VIN ≤ VIL,

Current—TTL Inputs

f = 0

Notes:

9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

10. TPower-up: Assumes a linear ramp from 0Vv to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05689 Rev. *E

Page 9 of 18

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