CY7C1364C
Pin Definitions (continued)
Name | TQFP | I/O | Description | ||
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VDDQ | 4, 11, 20, 27, 54, 61, 70, 77 | I/O Power | Power supply for the I/O circuitry. | ||
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VSSQ | 5, 10, 21, 26, 55, 60, 71, 76 | I/O Ground | Ground for the I/O circuitry. | ||
MODE | 31 | Input- | Selects Burst Order. When tied to GND selects linear burst sequence. | ||
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| Static | When tied to VDD or left floating selects interleaved burst sequence. | ||
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| This is a strap pin and should remain static during device operation. | ||
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| Mode pin has an internal | ||
NC | 1, 14, 16, 30, 38, 39, 42, |
| No Connects. Not internally connected to the die | ||
| 51, 66, 80 |
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Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.
The CY7C1364C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A
Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with
Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2)CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2)CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the RAM
array. The Write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle.
Because the CY7C1364C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi- tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a Write to the desired byte(s).
Because the CY7C1364C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will
Document #: | Page 5 of 18 |
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