CY7C1364C
Document #: 38-05689 Rev. *E Page 6 of 18

Burst Sequences

The CY7C1364C provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
Fourth
Address
A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Linear Burst Address Table (MODE = GND)

First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
Fourth
Address
A[1:0]
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 50 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ Active to Sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit Sleep current This parameter is sampled 0 ns
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