Cypress CY7C1364C Read/Write Cycle Timing

CY7C1364C

Document #: 38-05689 Rev. *E Page 14 of 18

Read/Write Cycle Timing[18,20, 21]

Notes:

20.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

21.GW is HIGH.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BW[A:D]

ata Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

[+] Feedback

Contents

Main CY7C1364C 9-Mbit ( 256K x 32 ) Pi Selection Guide CY7C1364C Pin Configuration 100-Pin TQFP Pinout (2 Chip Enables) (AJ version) CY7C1364C Document #: 38-05689 Rev. *E Page 3 of 18 Pin Configuration CY7C1364C 100-Pin TQFP Pinout (3 Chip Enables) (A version) CY7C1364C Pin Definitions Functional Overview Pin Definitions CY7C1364C Burst Sequences Sleep Mode Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) CY7C1364C Truth Table Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing CY7C1364C Write Cycle Timing Read/Write Cycle Timing ZZ Mode Timing Ordering Information Package Diagram A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Document History Page