Read/Write Cycle Timing18,20, Clz | Cypress CY7C1364C guide

CY7C1364C

Switching Waveforms (continued)

Read/Write Cycle Timing[18,20, 21]

			tCYC
CLK
		tCH	tCL
	tADS	tADH
ADSP
ADSC
	tAS	tAH
ADDRESS	A1	A2
BWE,
BW[A:D]
	tCES	tCEH
CE
ADV
OE
			tCO

A3 A4

tWES tWEH

tDS tDH

A5 A6

Data In (D)	High-Z	t	tOEHZ
		t	tOEHZ
		CLZ
Data Out (Q)	High-Z	Q(A1)	Q(A2)

D(A3)

tOELZ

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE	BURST READ
DON’T CARE	UNDEFINED

Back-to-Back

WRITEs

Notes:

20.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

21.GW is HIGH.

Document #: 38-05689 Rev. *E

Page 14 of 18

[+] Feedback

Image 14

Cypress CY7C1364C manual Read/Write Cycle Timing18,20, Clz

Contents

Cypress Semiconductor Corporation FeaturesFunctional Description1 250 MHz 200 MHz 166 MHz Unit Pin ConfigurationSelection Guide CY7C1364C Pin Tqfp Pinout 3 Chip Enables a version Pin Definitions Tqfp Functional Overview Burst Sequences Sleep ModeLinear Burst Address Table Mode = GND First Second Third Fourth Address Write Address Next Cycle UsedAdsp Adsc ADV BWE BW D BW C BW B BW a Truth Table for Read/Write3Function Operating Range Electrical Characteristics Over the Operating Range 9Maximum Ratings AC Test Loads and Waveforms Capacitance11Thermal Resistance Switching Characteristics Over the Operating Range12,13 Switching Waveforms Read Cycle Timing18 Write Cycle Timing18,19 ADV Read/Write Cycle Timing18,20 CLZ ZZ Mode Timing22 DON’T Care Ordering Information Package Diagram Pin Tqfp 14 x 20 x 1.4 mm REV ECN no Issue Date Orig. Description of ChangeDocument History