Cypress CY7C1365C CY7C1365C

CY7C1365C

Document #: 38-05690 Rev. *E Page 13 of 18

Read Cycle Timing[17]

Note:

17.On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

Data Out (Q) High-Z

tCLZ

tDOH

tCDV

tOEHZ

tCDV

Single READ BURST

READ

tOEV tOELZ tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2)Q(A2 + 3)

ADV suspends burst.

Deselect Cycle

DON’T CARE UNDEFINED

ADSP

ADSC

W, BWE,BW

[A:D]

ADV

[+] Feedback

Contents

Main 9-Mbit (256K x 32) Flow-Through Sync SRAM CY7C1365C Features Functional Description Selection Guide Logic Block Diagram-CY7C1365C (256K x 32) CY7C1365C Document #: 38-05690 Rev. *E Page 3 of 18 Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) CY7C1365C Pin Configurations CY7C1365C CY7C1365C Pin Descriptions CY7C1365C Pin Descriptions CY7C1365C Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1365C Timing Diagrams Read Cycle Timing Write Cycle Timing Read/Write Timing Ordering Information Package Diagram A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Document History Page