CY7C1365C

Timing Diagrams (continued)

ZZMode Timing [21, 22]

CLK

t ZZ

ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

Ordering Information

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

Ordering Code

Package

Package Type

Operating

(MHz)

Diagram

Range

 

 

 

 

 

133

CY7C1365C-133AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

 

 

 

(3 Chip Enable)

 

 

CY7C1365C-133AJXC

 

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

 

 

 

 

(2 Chip Enable)

 

 

CY7C1365C-133AXI

 

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

 

 

 

(3 Chip Enable)

 

 

CY7C1365C-133AJXI

 

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

 

 

 

 

(2 Chip Enable)

 

100

CY7C1365C-100AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

 

 

 

(3 Chip Enable)

 

 

CY7C1365C-100AJXC

 

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

 

 

 

 

(2 Chip Enable)

 

 

CY7C1365C-100AXI

 

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

 

 

 

(3 Chip Enable)

 

 

CY7C1365C-100AJXI

 

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

 

 

 

 

(2 Chip Enable)

 

Notes:

21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22.DQs are in High-Z when exiting ZZ sleep mode.

Document #: 38-05690 Rev. *E

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Cypress CY7C1365C manual Ordering Information, ZZ Mode Timing 21, DON’T Care