Cypress CY7C1365C Logic Block Diagram-CY7C1365C (256K x 32)

CY7C1365C

Document #: 38-05690 Rev. *E Page 2 of 18

ADDRESS

BURST

COUNTER

AND LOGIC

CLR

ENABLE

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE A

[1:0]

0, A1, A

ADV

CLK

ADSP

ADSC

BWD

BWC

BWB

BWA

BWE

CE1

CE2

CE3

SLEEP

CONTROL

DQA

BYTE

WRITE REGISTER

DQB

BYTE

WRITE REGISTER

DQC

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

DQC

BYTE

WRITE REGISTER

DQB

BYTE

WRITE REGISTER

DQA

BYTE

WRITE REGISTER

Logic Block Diagram-CY7C1365C (256K x 32)

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Contents

Main 9-Mbit (256K x 32) Flow-Through Sync SRAM CY7C1365C Features Functional Description Selection Guide Logic Block Diagram-CY7C1365C (256K x 32) CY7C1365C Document #: 38-05690 Rev. *E Page 3 of 18 Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) CY7C1365C Pin Configurations CY7C1365C CY7C1365C Pin Descriptions CY7C1365C Pin Descriptions CY7C1365C Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1365C Timing Diagrams Read Cycle Timing Write Cycle Timing Read/Write Timing Ordering Information Package Diagram A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Document History Page