Logic Block Diagram-CY7C1365C 256K x | Cypress specification

					CY7C1365C
Logic Block Diagram-CY7C1365C (256K x 32)
A0, A1, A	ADDRESS
A0, A1, A	REGISTER
	REGISTER
MODE		A[1:0]
MODE
ADV	BURST	Q1
CLK	COUNTER
	AND LOGIC
	CLR	Q0
	CLR
ADSC
ADSP
	DQD	DQD
BWD	DQD	BYTE
BWD	BYTE	BYTE
	BYTE	WRITE REGISTER
	WRITE REGISTER	WRITE REGISTER
	WRITE REGISTER
	DQC	DQC
BWC	DQC	BYTE
BWC	BYTE	BYTE
	BYTE	WRITE REGISTER
	WRITE REGISTER	WRITE REGISTER	MEMORY		OUTPUT	DQs
	WRITE REGISTER		MEMORY	SENSE	OUTPUT	DQs
			ARRAY	SENSE	BUFFERS
		DQB	ARRAY	AMPS	BUFFERS
	DQB	DQB		AMPS
BWB	DQB	BYTE
	BYTE	BYTE
		WRITE REGISTER

	WRITE REGISTER
	WRITE REGISTER
		DQA
BWA	DQA	BYTE
BWA	BYTE	WRITE REGISTER
BWE	BYTE	WRITE REGISTER
BWE	WRITE REGISTER
	WRITE REGISTER
GW					INPUT
CE1	ENABLE				REGISTERS
	ENABLE
	REGISTER
CE2	REGISTER
CE2
CE3
OE
ZZ	SLEEP
ZZ	CONTROL
	CONTROL

Document #: 38-05690 Rev. *E

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Cypress manual Logic Block Diagram-CY7C1365C 256K x

Contents

133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor Corporation Logic Block Diagram-CY7C1365C 256K x CY7C1365C Pin Configurations 15CY7C1365C Pin Tqfp Pinout 3 Chip Enable a version Pin Descriptions Tqfp Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Functional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Address Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Adsp Adsc ADV Write CLK BWE BW D BW C BW B BW a Truth Table for Read/Write3Function Ambient Range Maximum RatingsOperating Range GND ≤ V I ≤ V DDQ Thermal Resistance10 AC Test Loads and Waveforms Switching Characteristics Over the Operating Range11 Timing Diagrams Read Cycle Timing17 Write Cycle Timing18 Read/Write Timing17, 19 DON’T Care ZZ Mode Timing 21Ordering Information Package Diagram Pin Tqfp 14 x 20 x 1.4 mm REV ECN no Issue Date Orig. Description of ChangeDocument History