Cypress CY7C1365C manual ZZ Mode Electrical Characteristics, Address Cycle Description Used

CY7C1365C

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD – 0.2V

50

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2V

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

ns

tZZI

ZZ Active to Sleep current

This parameter is sampled

2tCYC

ns

tRZZI

ZZ Inactive to exit Sleep current

This parameter is sampled

0

ns

Truth Table[3, 4, 5, 6, 7]

Address

Cycle Description

Used

CE

1

CE

3

CE2

ZZ

ADSP

ADSC

ADV

WRITE

OE

CLK

DQ

Deselected Cycle,

None

H

X

X

L

X

L

X

X

X

L-H

Tri-State

Power-down

Deselected Cycle,

None

L

X

L

L

L

X

X

X

X

L-H

Tri-State

Power-down

Deselected Cycle,

None

L

H

X

L

L

X

X

X

X

L-H

Tri-State

Power-down

Deselected Cycle,

None

L

X

L

L

H

L

X

X

X

L-H

Tri-State

Power-down

Deselected Cycle,

None

X

X

X

L

H

L

X

X

X

L-H

Tri-State

Power-down

Sleep Mode, Power-down

None

X

X

X

H

X

X

X

X

X

X

Tri-State

Read Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

L

L-H

Q

Read Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

H

L-H

Tri-State

Write Cycle, Begin Burst

External

L

L

H

L

H

L

X

L

X

L-H

D

Read Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

L

L-H

Q

Read Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

H

L-H

Tri-State

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H

Q

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H

Tri-State

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H

Q

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H

Tri-State

Write Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H

D

Write Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H

D

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

L

L-H

Q

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

H

L-H

Tri-State

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L-H

Q

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

H

L-H

Tri-State

Write Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H

D

Write Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H

D

Notes:

3.X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4.WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB, BWC, BWD), BWE, GW = H.

5.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6.The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the Write cycle.

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05690 Rev. *E Page 8 of 18

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