Cypress CY7C1365C Write Cycle Timing

CY7C1365C

Document #: 38-05690 Rev. *E Page 14 of 18

Write Cycle Timing[18, 19]

Notes:

18.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

19.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

Timing Diagrams (continued)

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

High-Z

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for first cycle when

ADSP initiates burst.

ADSC extends burst.

ADV suspends burst.

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

BW[A:D]

ADV

Data in (D)

ata Out (Q)

[+] Feedback

Contents

Main 9-Mbit (256K x 32) Flow-Through Sync SRAM CY7C1365C Features Functional Description Selection Guide Logic Block Diagram-CY7C1365C (256K x 32) CY7C1365C Document #: 38-05690 Rev. *E Page 3 of 18 Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) CY7C1365C Pin Configurations CY7C1365C CY7C1365C Pin Descriptions CY7C1365C Pin Descriptions CY7C1365C Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1365C Timing Diagrams Read Cycle Timing Write Cycle Timing Read/Write Timing Ordering Information Package Diagram A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Document History Page