Power supply inputs to the core of the device

			CY7C1365C
			CY7C1365C


Pin Descriptions (continued)

Name	TQFP	I/O	Description

VDD	15,41,65, 91	Power Supply	Power supply inputs to the core of the device.
VSS	17,40,67,90	Ground	Ground for the core of the device.
VDDQ	4,11,20,27,54,61,70,77,	I/O Power	Power supply for the I/O circuitry.
		Supply
VSSQ	5,10,21,26,55,60,71,76	I/O Ground	Ground for the I/O circuitry.
MODE	31	Input-	Selects Burst Order. When tied to GND selects linear burst
		Static	sequence. When tied to VDD or left floating selects interleaved burst
			sequence. This is a strap pin and should remain static during device
			operation. Mode Pin has an internal pull-up.
NC	1,30,51,80,14,16,38,39,42,66		No Connects. Not Internally connected to the die.
	43 (for 2 Chip Enable Version)

Document #: 38-05690 Rev. *E

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Contents

133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor Corporation Logic Block Diagram-CY7C1365C 256K x CY7C1365C Pin Configurations 15CY7C1365C Pin Tqfp Pinout 3 Chip Enable a version Pin Descriptions Tqfp Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDFunctional Overview Address Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Adsp Adsc ADV Write CLK Truth Table for Read/Write3 FunctionBWE BW D BW C BW B BW a Ambient Range Maximum RatingsOperating Range GND ≤ V I ≤ V DDQ Thermal Resistance10 AC Test Loads and Waveforms Switching Characteristics Over the Operating Range11 Timing Diagrams Read Cycle Timing17 Write Cycle Timing18 Read/Write Timing17, 19 ZZ Mode Timing 21 Ordering InformationDON’T Care Package Diagram Pin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document HistoryREV ECN no

Cypress CY7C1365C Power supply inputs to the core of the device, Ground for the I/O circuitry